Functional Description Simplified State Diagram from any state Power Applied MPSM IVREFDQ, RTT,Etc MRS SRX w/NOP MRS SRX w/ NOP MRS MRS,MPR, w/ Q=Low Initialization PDA Write Leveling Reset Procedure ZQCL RESET Connectivity Test Precharge Power Down CKE_L Active Power Down Read WriteA ReadA Read Write WriteA ReadA Automatic Sequence Command Sequence Enter Power-down Exit Power-down Self-Refresh entry Self-Refresh exit Refresh, Fine granularity Refresh Start RESET procedure Multi Purpose Register Boundary Scan Mode Enable NOTE 1 This simplified State Diagram is intended to provide an overview...

Basic Functionality The DDR4 SDRAM is a high-speed dynamic random-access memory internally configured as sixteen-banks, 4 bank group with 4 banks for each bank group for x4/x8 and eight-banks, 2 bank group with 4 banks for each bankgroup for x16 DRAM. The DDR4 SDRAM uses a 8n prefetch architecture to achieve high-speed operation. The 8n prefetch architecture is combined with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write operation for the DDR4 SDRAM consists of a single 8n-bit wide, four clock data transfer at the internal DRAM core and...

RESET and Initialization Procedure For power-up and reset initialization, in order to prevent DRAM from functioning improperly default values for the following MR settings need to be defined. Gear down mode (MR3 A[3]) : 0 = 1/2 Rate Per DRAM Addressability (MR3 A[4]) : 0 = Disable Max Power Saving Mode (MR4 A[1]) : 0 = Disable CS to Command/Address Latency (MR4 A[8:6]) : 000 = Disable CA Parity Latency Mode (MR5 A[2:0]) : 000 = Disable Hard Post Package Repair mode (MR4 A[13]) : 0 = Disable Soft Post Package Repair mode (MR4 A[5]) : 0 = Disable Power-up Initialization Sequence The following sequence...

Static LOW in case RTT_Nom is eanbled at time Tg, otherwise static HIGH or LOW TIME BREAK DON’T CARE NOTE 1 From time point ‘Td’ until ‘Tk’, DES commands must be applied between MRS and ZQCL commands. NOTE 2 MRS Commands must be issued to all Mode Registers that have defined settings. Figure 1 — RESET_n and Initialization Sequence at Power-on Ramping VDD Slew rate at Power-up Initialization Sequence Table 1 — VDD Slew Rate Symbol a. Measurement made between 300mV and 80% Vdd minimum. b. 20 MHz bandlimited measurement. c. Maximum time to ramp VDD from 300mV to VDD

Reset Initialization with Stable Power The following sequence is required for RESET at no power interruption initialization as shown in Figure 2. 1. Asserted RESET_n below 0.2 * VDD anytime when reset is needed (all other inputs may be undefined). RESET_n needs to be maintained for minimum tPW_RESET. CKE is pulled "LOW" before RESET_n being de-asserted (min. time 10 ns). 2. Follow steps 2 to 10 in "Power-up Initialization Sequence" on page 8. 3. The Reset sequence is now completed, DDR4 SDRAM is ready for Read/Write training (include Vref training and Write leveling) Ta VALID tXPR tZQin tDLLK...

^ TIME BREAK □ DON'T CARE NOTE 1 This timing diagram shows C/A Parity Latency mode is “Disable” case. NOTE 2 List of MRS commands exception that do not apply to tMRD - Gear down mode - C/A Parity Latency mode - CS to Command/Address Latency mode - Per DRAM Addressability mode - VrefDQ training Value, VrefDQ Training mode and VrefDQ training Range Figure 3 — tMRD Timing Some of the Mode Register setting affect to address/command/control input functionality. These case, next MRS command can be allowed when the function updating by current MRS command completed. The MRS commands which do not apply...

NOTE 1 This timing diagram shows CA Parity Latency mode is “Disable” case. NOTE 2 List of MRS commands exception that do not apply to tMOD - DLL Enable, DLL Reset - VrefDQ training Value, internal Vref Monitor, VrefDQ Training mode and VrefDQ training Range - Gear down mode - Per DRAM addressability mode - Maximum power saving mode - CA Parity mode Figure 4 — tMOD Timing Some of the mode register setting cases, function updating takes longer than tMOD. The MRS commands which do not apply tMOD timing to next valid command excluding DES is listed in note 2 of Figure 9. These MRS command input cases...

RTT_NOM tADC_min tADC_min tADC_max NOTE 1 NOTE 1 This timing diagram shows CA Parity Latency mode is “Disable” case. NOTE 2 NOTE 2 When an MRS command mentioned in this note affects RTT_NOM turn on timings, RTT_NOM turn off timings and RTT_NOM value, this means the MR register value changes. The ODT signal should set to be low for at least DODTLoff +1 clock before their affecting MRS command is issued and remain low until tMOD expires. The following MR registers affects RTT_NOM turn on timings, RTT_NOM turn off timings and RTT_NOM value and it requires ODT to be low when an MRS command change...

SK hynix Table 3 — CAS Latency

Table 6 — DDR4 MR Bit Allocation for Rx EQ Control

NOTE : 1. The 2 tCK Write Preamble is valid for DDR4-2400/2666/2933/3200 Speed Grade. For the 2nd Set of 2 tCK Write Preamble, no additional CWL is needed.

NOTE : 1. Write Command latency when CRC and DM are both enabled: 2. At less than or equal to 1600 then 4nCK; neither 5nCK nor 6nCK 3. At greater than 1600 and less than or equal to 2666 then 5nCK; neither 4nCK nor 6nCK 4. At greater than 2666 and less than or equal to 3200 then 6nCK; neither 4nCK nor 5nCK

Table 11 — MPR Data Format NOTE : 1. MPR used for C/A parity error log readout is enabled by setting A[2] in MR3 2. For higher density of DRAM, where A[17] is not used, MPR2[1] should be treated as don’t care. 3. If a device is used in monolithic application, where C[2:0] are not used, then MPR3[2:0] should be treated as don’t care. 4. MPR3 bit 0~2 (CA parity latency) reflects the latest programmed CA parity latency values.

NOTE : 1. MPR page3 is specifically assigned to DRAM. Actual encoding method is vendor specific.