DDR2 SDRAM Device Operations
DDR2 SDRAM Device Operations
- Simplified State Diagram: Describes state transitions and command sequences for DDR2 SDRAM, including activation, reading, writing, and power management.
- Basic Function & Operation: DDR2 SDRAM operations are burst-oriented, requiring initialization steps such as power-up, mode register programming, and calibration.
- Power Up and Initialization: A specific sequence is necessary for proper DDR2 SDRAM operation.
- Programming Mode and Extended Mode Registers: These registers control operational parameters like burst length and CAS latency, essential for device functionality.
- Includes command and clock enable truth tables for synchronous transistors, aiding in command execution and timing.
- Details absolute maximum DC ratings and operating temperature conditions for device reliability.
- Specifies recommended DC operating conditions, logic input levels, and output buffer levels, including overshoot/undershoot specifications.
- Initialization Sequence Diagram: Visualizes the power-up and initialization sequence, highlighting timing requirements.
- Mode Register Set (MRS) Diagram: Details mode register configuration, including CAS latency and burst length.
- Extended Mode Register (EMR) Programming: Outlines settings for DLL, output driver strength, and other features.
Discusses DDR2 SDRAM features like Partial Array Self Refresh (PASR) and Duty Cycle Corrector (DCC), with EMR settings crucial for enabling these features.
Procedures:
Outlines programming of EMR(2) and EMR(3) for DDR2 SDRAM, controlling PASR and DCC.
OCD Impedance Adjustment:
Supports Off-Chip Driver (OCD) impedance adjustment for driver strength calibration.
On Die Termination (ODT):
Improves signal integrity by enabling/disabling termination resistance, applicable in active and standby modes.
Bank Activate Command:
Essential for initiating read/write operations, with timing constraints like tRCDmin, tRAS, and tRP.
Read and Write Access Modes:
Executed after bank activation, with specific command settings and timing constraints like tCCD.
Posted CAS:
Enhances command and data bus efficiency by allowing CAS commands during RAS-CAS delay.
Burst Mode Operation: Supports 4-bit and 8-bit burst modes, with critical parameters like burst sequence and length.
Burst Read Command: Timing defined by read latency (RL), synchronized with the data strobe signal (DQS).
Burst Write Operation: Defined by write latency (WL), with timing requirements and data strobe signal role detailed.
Precharge Operation: Used to close an activated bank, with conditions and timing for issuing a precharge command outlined.
Key Timing Parameters: Provides timing diagrams and tables illustrating command and operation relationships.
Interruptions and Limitations: Rules govern burst operation interruptions to ensure data integrity.
1. Burst Read and Write Operations: Supports burst operations with timing parameters like RL, AL, CL, BL, and tRTP.
2. Auto Precharge Operation: Allows automatic precharging during burst cycles, improving performance.
3. Burst Read/Write with Auto Precharge: Precharge begins after burst completion, with timing conditions met.
4. Refresh Commands: Requires periodic refreshes for data integrity, using Auto or Self Refresh commands.
5. Power-Down Mode: Reduces power consumption when idle, with DLL state considerations.
6. Timing Diagrams: Illustrates command sequences and timing relationships for various operations.
Power-Down Modes: Supports precharge and active power-down modes, with DLL state considerations.
Command Operations: Outlines various command operations, including NOP and Deselect commands.
Timing Diagrams: Illustrates power-down mode entry/exit, read/write operations, and clock frequency changes.
Electrical Characteristics: Specifies DC ratings and operating temperature conditions, emphasizing VDD, VDDQ, and VDDL limits.
Key Parameters: Provides recommended DC operating conditions and measurement definitions for Rtt and VM.
1. VDDQ must be ≤ VDD.
2. VREF adjustable for noise margin, typically 0.5 x VDDQ.
3. VREF AC noise should not exceed +/-2% of VREF (dc).
4. VTT must track VREF of the receiving device.
5. VDDQ and VDDL should track with VDD.
Impedance Values:
Rtt values vary based on EMRS settings.
AC & DC Operating Conditions:
Defines DC input logic levels and AC input logic levels with test conditions.
Differential Input and Output Parameters:
Defines differential input/output parameters, including overshoot/undershoot specifications.
Power and Ground Clamps:
Details voltage and current characteristics for specific input pins.
Output Buffer Characteristics:
Specifies AC test conditions and DC current drive capabilities.
Calibrated Output Driver Characteristics:
Emphasizes system calibration for maintaining performance within bounds.
Catalog excerpts
DDR2 Device Operations & Timing Diagram
Open the catalog to page 1
DDR2 Device Operations & Timing Diagram Contents 1. Functional Description 1.1 Simplified State Diagram 1.2 Basic Function & Operation of DDR2 SDRAM 1.2.1 Power up and Initialization 1.2.2 Programming the Mode and Extended Mode Registers 1.2.2.1 DDR2 SDRAM Mode Register (MR) 1.2.2.2 DDR2 SDRAM Extended Mode Register 1.2.2.3 Off-Chip Driver(OCD) Impedance Adjustment 1.2.2.4 ODT(On Die Termination) 1.3 Bank Activate Command 1.4 Read and Write Command 1.4.1 Posted CAS 1.4.2 Burst Mode Operation 1.4.3 Burst Read Command 1.4.4 Burst Write Operation 1.4.5 Write Data Mask 1.5 Precharge Operation 1.6...
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DDR2 Device Operations & Timing Diagram 1. Functional Description 1.1 Simplified State Diagram Initialization Sequence CKEL OCD calibration Self Refreshing SRF CKEH CKEH Precharge Power Down CKEL Automatic Sequence Active Power Down Command Sequence CKEH CKEL Bank Active WRA WRA Writing with Autoprecharge Reading with Autoprecharge CKEL = CKE LOW, enter Power Down CKEH = CKE HIGH, exit Power Down, exit Self Refresh ACT = Activate WR(A) = Write (with Autoprecharge) RD(A) = Read (with Autoprecharge) PR(A) = Precharge (All) (E)MR = (Extended) Mode Register SRF = Enter Self Refresh REF = Refresh...
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DDR2 Device Operations & Timing Diagram 1.2 Basic Function & Operation of DDR2 SDRAM Read and write accesses to the DDR2 SDRAM are burst oriented; accesses start at a selected location and continue for a burst length of four or eight in a programmed sequence. Accesses begin with the registration of an Active command, which is then followed by a Read or Write command. The address bits registered coincident with the active command are used to select the bank and row to be accessed (BA0-BA2 select the bank; A0-A15 select the row). The address bits registered coincident with the Read or Write command...
Open the catalog to page 4
DDR2 Device Operations & Timing Diagram If OCD calibration is not used, EMR OCD Default command (A9=A8= A7=1) followed by EMR OCD Calibration Mode Exit command (A9=A8=A7=0) must be issued with other operating parameters of EMR. 13. The DDR2 SDRAM is now ready for normal operation. *1) To guarantee ODT off, VREF must be valid and a LOW level must be applied to the ODT pin. *2) Sequence 5 and 6 may be performed between 8 and 9. Initialization Sequence after Power Up tCH tCL Figure 2. Initialization sequence after power-up 1.2.2 Programming the Mode and Extended Mode Registers For application flexibility,...
Open the catalog to page 5
1.2.2.1 DDR2 SDRAM Mode Register (MR) The mode register stores the data for controlling the various operating modes of DDR2 SDRAM. It controls CAS latency, burst length, burst sequence, test mode, DLL reset, WR and various vendor specific options to make DDR2 SDRAM useful for various applications. The default value of the mode register is not defined, therefore the mode register must be programmed during initialization for proper operation. The mode register is written by asserting LOW on CS, RAS, CAS, WE, BA0 and BA1, while controlling the state of address pins A0 ~ A15. The DDR2 SDRAM should...
Open the catalog to page 6
DDR2 Device Operations & Timing Diagram 1.2.2.2 DDR2 SDRAM Extended Mode Register EMR(1) The extended mode register(1) stores the data for enabling or disabling the DLL, output driver strength, additive latency, ODT, DQS disable, OCD program, RDQS enable. The default value of the extended mode register(1) is not defined, therefore the extended mode register(1) must be programmed during initialization for proper operation. The extended mode register(1) is written by asserting LOW on CS, RAS, CAS, WE, HIGH on BA0 and LOW on BA1, while controlling the states of address pins A0 ~ A15. The DDR2 SDRAM...
Open the catalog to page 7
Address Field * 3 : When Adjust mode is issued, AL from previously set value must be applied * 4 : After setting to default, OCD mode needs to be exited by setting A9-A7 to 000. Refer to the following 1.2.2.3 section for detailed information *5. Outputs disabled - DQs, DQSs, DQSs, RDQS, RDQS. This feature is used in conjunction with DIMM IDD meaurements when IDDQ is not desired to be included. *6. If RDQS is enabled, the DM function is disabled. RDQS is active for reads and don't care for writes. *1 : BA2 and A13~A15 are reserved for future use and must be set to 0 when programming the EMR(1)
Open the catalog to page 8
DDR2 Device Operations & Timing Diagram SK^ynix EMR(2) The extended mode register(2) controls refresh related features. The default value of the extended mode register^) is not defined, therefore the extended mode register(2) must be programmed during initialization for proper operation. The extended mode register(2) is written by asserting LOW on /CS,/RAS,/CAS,/WE, HIGH on BA1 and LOW on BAO, while controling the states of address pins A0~A15. The DDR2 SDRAM should be in all bank precharge with CKE already HIGH prior to writing into the extended mode register(2). The mode register set command...
Open the catalog to page 9
DDR2 Device Operations & Timing Diagram SK^ynix EMR(3) No function is defined in extended mode register(3). The default value of the extended mode register(3) is not defined, therefore the extended mode register(3) must be programmed during initialization for proper operation. Address Field Extended Mode Register(2) *1 :All bits in EMR(3) except BA0 and BA1 are reserved for future use and must be programmed to 0 when setting the mode register during initialization.
Open the catalog to page 10
DDR2 Device Operations & Timing Diagram 1.2.2.3 Off-Chip Driver (OCD) Impedance Adjustment DDR2 SDRAM supports driver calibration feature and the flow chart below is an example of sequence. Every calibration mode command should be followed by “OCD calibration mode exit” before any other command being issued. All MR should be programmed before entering OCD impedance adjustment and ODT (On Die Termiantion) should be carefully controlled depending on system environment. All MR shoud be programmed before entering OCD impedance adjustment and ODT should be carefully controlled depending on system...
Open the catalog to page 11
DDR2 Device Operations & Timing Diagram Extended Mode Register for OCD impedance adjustment OCD impedance adjustment can be done using the following EMR mode. In drive mode all outputs are driven out by DDR2 SDRAM and drive of RDQS is depedent on EMR bit enabling RDQS operation. In Drive(1) mode, all DQ, DQS (and RDQS) signals are driven HIGH and all DQS signals are driven LOW. In drive(0) mode, all DQ, DQS (and RDQS) signals are driven LOW and all DQS signals are driven HIGH. In adjust mode, BL = 4 of operation code data must be used. In case of OCD calibration default, output driver characteristics...
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