Rev. 1.4 12/10 Copyright © 2010 by Silicon Laboratories Si3000 Si3000 VOICEBAND CODEC WITH MICROPHONE/SPEAKER DRIVE Features Complete voice codec solution includes the following: Applications Description The Si3000 is a complete voice band audio codec solution that offers high integration by incorporating programmable input and output gain/attenuation, a microphone bias circuit, handset hybrid circuit, and an output drive for 32 ƒÇ headphones. The Si3000 can be connected directly to the Si3034, Si3035, Si3044, and Si3056 North American and international DAA chipsets through their daisy-chaining serial interface. It also serves as a companion chip to a FAT ISOmodem chipset with voice features, providing hardware support for a handset and speaker phone. The device operates from a single 3.3 to 5 V power supply and is available in a 16-pin small outline package (SOIC). Functional Block Diagram ƒÞ84 dB ADC Dynamic Range ƒÞ84 dB DAC Dynamic Range ƒÞ4–12 kHz Sample Rates ƒÞ30 dB Microphone Pre-Amp ƒÞProgrammable Input Gain/Attenuation: –34.5 dB to 12 dB ƒÞProgrammable Output Gain/Attenuation: –34.5 dB to 12 dB ƒÞSupport for 32 ƒÇ Headphones ƒÞ3:1 Analog Input Mixer ƒÞ3.3–5.0 V Power Supply ƒÞDirect Serial Interface to DSPs ƒÞDirect Connection to Si303x/44/56, serial interface DAA chipsets ƒÞLow profile 16-Pin SOIC Package ƒÞRoHS-compliant package available ƒÞModem Voice Channel (DSVD) ƒÞTelephony ƒÞSpeech Processing ƒÞGeneral Purpose Analog I/O ƒÞCompanion chip for FDX ISOmodems with voice features Digital InterfaceProg Gain/AttenuatorADCDACHandset HybridHeadphone DriverHigh Pass Filter0/+10/+20/+30 dB0/+10/+20 dB0/–6/–12/–18 dB0/–6/–12/–18 dBMBIASMICLINEIHDSTSPKRRSPKRLLINEOMCLKSCLKFSYNCSDISDORESETProg Gain/AttenuatorSi3000 Ordering Information: See page 29. Pin Assignments Si3000 21345678151614131211109SPKRRMBIASHDSTSDISDOMCLKSCLKLINEOGNDVAVDLINEIMICRESETSPKRLFSYNC

Si3000 Rev. 1.4 3 TABLE OF CONTENTS Section Page 1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 2.1. Analog Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 2.2. Pre-amp/Microphone Bias Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 2.3. Programmable Input Gain/Attenuation ....

Si3000 4 Rev. 1.4 1. Electrical Specifications Table 1. Recommended Operating Conditions Parameter Symbol Test Condition Min1 Typ Max1 Unit Ambient Temperature TA F and K-grade 0 25 70 °C Si3000 Supply Voltage, Analog2 VA 3.0 3.3/5.0 5.25 V Si3000 Supply Voltage, Digital2,3 VD 3.0 3.3/5.0 5.25 V Notes: 1.All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. Typical values apply at nominal supply voltages and an operating temperature of 25°C unless otherwise stated. 2. The digital supply, VD, and analog supply, VA, can operate from either...

Si3000 Rev. 1.4 5 Table 4. AC Characteristics (VA, VD = 5 V ±5% or 3.3 V ±10%, TA = 0 to 70°C) Parameter Symbol Test Condition Min Typ Max Unit ADC Resolution — 16 — Bits ADC Dynamic Range1,2 ADCDR VIN = 1 kHz, –3 dB 80 84 — dB ADC Total Harmonic Distortion3 ADCTHD VIN = 1 kHz, –3 dB, MIC/LINEI — –80 –62 dB VA, VD = 3.3 V ±10% VIN = 1 kHz, –3 dB, HDST — –80 –62 ADC Total Harmonic Distortion3 ADCTHD VIN = 1 kHz, –3 dB, MIC/LINEI — –80 –76 dB VA, VD = 5 V ±5% VIN = 1 kHz, –3 dB, HDST — –80 –71 ADC Full Scale Level (0 dB gain)4 VRX Vin = 1 kHz — 1 — Vrms ADC Programmable Input Gain –34.5 — 12 dB...

Si3000 6 Rev. 1.4 DAC Output Gain Step Size — 1.5 — dB DAC Freq Response5 FRR Low –3 dB corner — 33 — Hz DAC Freq Response5 FRR 300 Hz –0.01 — 0 dB DAC Freq Response FRR 3400 Hz –0.2 — 0 dB DAC Line Output Load Resistance 600 — — ƒÇ DAC Line Output Load Capacitance — — 40 pF DAC SPKR Output Load Resistance — 60 — ƒÇ DAC Gain Drift AT VIN = 1 kHz — 0.002 — dB/°C Interchannel Isolation (Crosstalk) — 90 — dB HDST Full Scale Level Input — 0.5 — Vrms HDST Full Scale Level Output6 — 1.0 — Vrms HDST Output Resistance Rout DC — 600 — ƒÇ MIC Bias Voltage Vmbias — 2.5 — V MIC Power Supply Rejection Ratio...

Si3000 Rev. 1.4 7 Figure 1. General Inputs Timing Diagram Table 6. Switching Characteristics—General Inputs (VA, VD = 5 V ±5% or 3.3 V ±10%,TA = 0 to 70°C, CL = 20 pF) Parameter1 Symbol Test Condition Min Typ Max Unit Cycle Time, MCLK tmc 16.67 — — ns MCLK Duty Cycle tdty 40 50 60 % Rise Time, MCLK tr — — 5 ns Fall Time, MCLK tf — — 5 ns RESET Pulse Width2 trl 250 — — ns Rise Time, RESET tRr — 1 — ìs Notes: 1.All timing (except Rise and Fall time) is referenced to the 50% level of the waveform. Input test levels are VIH = VD – 0.4 V, VIL = 0.4 V. Rise and Fall times are referenced to the 20%...

Si3000 8 Rev. 1.4 Figure 2. Serial Interface Timing Diagram Table 7. Switching Characteristics—Serial Interface (VA, VD = 5 V ±5% or 3.3 V ±10%, TA = 0 to 70°C, CL = 20 pF) Parameter Symbol Test Condition Min Typ Max Unit Cycle Time, SCLK tc 354 1/256 Fs — ns SCLK Duty Cycle tdty — 50 — % Delay Time, SCLK „^ƒnto FSYNC „` td1 — — 10 ns Delay Time, SCLK „^ to SDO Valid td2 — — 20 ns Delay Time, SCLK „^ƒnto FSYNC „^ td3 — — 10 ns Setup Time, SDI, before SCLK „` tsu 25 — — ns Hold Time, SDI, after SCLK „` th 20 — — ns Setup Time, FSYNC (mode 2) before MCLK „` tsu 25 — — ns Hold Time, FSYNC (mode...