
Silicon Laboratories’ Any-Rate Precision Clocks offer clock multiplication, jitter attenuation, and clock distribution for high-performance timing applications. They accept multiple clock inputs from 2 kHz to 710 MHz and generate outputs from 2 kHz to 945 MHz, with select frequencies up to 1.4 GHz. These devices use DSPLL® technology for any-rate frequency synthesis and 0.3 psRMS jitter performance, eliminating the need for external VCXO and loop filter components.
Innovative DSPLL TechnologyDSPLL technology uses digital signal processing to move analog PLL functions into the digital domain, integrating components like VCO, loop filter, and phase detector on-chip, improving noise immunity and reducing BOM costs.
High PerformanceThe Si53xx series offers industry-leading jitter performance of 0.3 psRMS, rivaling discrete analog PLL technology.
Highly IntegratedThe Si53xx integrates all key PLL components, supporting up to four clock inputs and five differential outputs, eliminating the need for external muxes and buffers.
Easy-to-UseThe Si53xx is reconfigurable via pins or I2C/SPI interface, simplifying design reuse and integrating system-level clock features like hitless switching and programmable output phase control.
Product Specifications| Part Number | Clock Inputs | Clock Outputs | Jitter Gen | Programmable Loop Bandwidth | Clock Multiplication | Hitless Switching | Alarms | Package |
|---|---|---|---|---|---|---|---|---|
| Si5316 | 2 | 1 | 0.3 psRMS typ | 60 Hz – 8.4 kHz | — | — | LOL, LOS | 6x6 mm, 36-pin QFN |
| Si5323 | 2 | 2 | 0.3 psRMS typ | 60 Hz – 8.4 kHz | Yes | Yes | LOL, LOS | 6x6 mm, 36-pin QFN |
| Si5326 | 2 | 2 | 0.3 psRMS typ | 60 Hz – 8.4 kHz | Yes | Yes | LOL, LOS, FOS | 6x6 mm, 36-pin QFN |
| Si5366 | 4 | 5 | 0.3 psRMS typ | 60 Hz – 8.4 kHz | Yes | Yes | LOL, LOS, FOS | 14x14 mm, 100-pin TQFP |
| Si5368 | 4 | 5 | 0.3 psRMS typ | 60 Hz – 8.4 kHz | Yes | Yes | LOL, LOS, FOS | 14x14 mm, 100-pin TQFP |
DSPLLsim is a PC-based software utility for device selection and configuration, determining valid frequency plans and optimal PLL settings.
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