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Xpedition Substrate Integrator

Xpedition Substrate Integrator
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Xpedition Substrate Integrator Benefits • Rapid planning, prototyping and optimization of 2.5/3D heterogeneously integrated die/chiplets based semiconductor package assemblies • System connectivity management and visualization with cross-domain pin/signal mapping/shorting and system-level logical verification Introduction Xpedition® Substrate Integrator (xSI) provides a graphical, rapid virtual prototyping environment tuned for the exploration and integration of multiple heterogeneous ICs/chiplets and interposers into High Density Advanced Packages (HDAP). It utilizes a System Technology Co-Optimization (STCO) methodology to co-design complex 2.5/3D package assemblies while targeting different system PCBs. Designers and micro-architects can quickly and easily assemble complete cross-domain substrate systems and drive ball map plans and pin optimization through a rule-based methodology. Using an STCO methodology ensures ICs, packages, and PCBs are optimized in the context of each other. This results in fewer layers and tighter control of the design process resulting in optimized device performance, lower-cost package assemblies and PCBs with the benefit of system level performance. • User-definable rules for custom optimization of pin and ball-out assignments • Single-window visualization and hierarchical management of multi- die/ chiplet and substrate assemblies • Pin-based interface planning with or without nets. • Extensive input and output data formats • System-level LVS/STA verification through Calibre® 3DSTACK • Integration with Xpedition Package Designer and Calibre, for detailed implementation, verification, and signoff Figure 1: Complex heterogeneous 2.5/3D assemblies can be defined, managed and optimized for one or multiple target system PCBs

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Xpedition Substrate Integrator Targeting Multiple System Platforms With One Semiconductor Package A company designing semiconductors for smart, wireless, mobile products might want to target the same package configuration for use in several devices, such as a tablet, a laptop, a smart phone, etc. (Figure 1). The physical constraints for each application are significantly different, and the electrical constraints can also be different. Using xSI, this process is efficient and takes just a fraction of the time it would take to do manually, if it could be done at all. Package configurations...

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Prototyping & Planning Determining the best package based on cost and performance often requires the development of a custom package definition. In some cases, this can be a simple case of ball/pin depopulation. As an example, a CPU or GPU may require a completely asymmetrical array of pins to satisfy its market needs. Shown in Figure 3, xSI contains powerful capabilities to dynamically add, delete, copy, move, and adjust pin pitch. Heterogeneous Integration and Co-optimization Virtual Die Models (VDM) enable early asynchronous planning and optimization of ASICs or chiplets by...

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Rules Driven Pin Planning An easy-to-use pin planning and optimization rules engine lets engineers define which pins on the package can have which signals or interfaces assigned to them. Rules can also be written to ensure that critical nets are assigned adjacent to ground nets or that corner pins will only accept the ground signal. Figure 6 shows how rules are reflected in colors that designate which rule applies to a particular ball. Several types of rules are illustrated. For example, if data busses were not allowed on inner pins, any attempt to do so would result in an error reflected...

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