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Vista Virtual Prototyping

Vista Virtual Prototyping
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Electronic System Level Design DATASHEET Integrate and Optimize SW on Fast Simulation Model Host Machine KEY BENEFITS ■ Industry standard SystemC TLM 2.0 virtual prototype executable ■ Validation of software against early hardware model ■ Visibility of key hardware registers and attributes ■ Fast software execution speed ■ Support for large TLM models and platforms ■ Advanced product performance and power analysis ■ Non-intrusive trace, profiling and coverage ■ Intuitive software debug environment based on Sourcery™ CodeBench ■ Embedded software analysis based on Sourcery™ Analyzer With software development becoming the fastest growing component of NRE costs for both SoC and final product development, the challenges of developing, integrating, validating, and optimizing software in the context of hardware dominates the embedded design process. Thus it has become a necessity to make a fast, accurate, low-cost simulation model of the hardware available early to the embedded software team. Part of the Mentor Vista™ platform, Vista Virtual Prototyping provides an early, abstract functional model of the hardware to software engineers even before the hardware design is implemented in RTL. It can run software on embedded processor models at speeds par with physical hardware boards; yet it provides additional capabilities and benefits, such as the visibility and control to debug complex software/hardware interactions and optimize the software to meet final product performance and power goals. Platform Creation Transaction-level modeling (TLM) is an abstracted approach to modeling functional units of digital systems, whereby the details of communication among units are separated from the implementation details of the units. A TLM platform is composed of interconnected transaction-level models represented by SystemC structural code. Vista contains a library of pre-defined TLMs and allows users to customize key attributes (such as timing and power) in these models. Vista also enables users to create their own TLMs or import external models and add these to the Vista model library. TLM Platform Creation The Vista Block Diagram editor provides a simple way to create TLM platform SystemC structural code and link graphical symbols of individual TLMs to each other, thus defining the topology of the design. Upon each save operation, the Block Diagram editor automatically generates the structural code corresponding to the schematic view. The Block Diagram editor supports a wide range of operations, including selecting individual elements or groups; defining attributes and default names for graphic elements; resizing, moving, and copying elements; and editing symbols in either a symbol editor or the Block Diagram editor. It also allows users to rotate, delete, and duplicate graphics; add and edit text; and add TLM symbols. Block Diagram editor functions are readily accessed from menus, toolbars, and sidebars, providing flexibility and ease-of-use for TLM platform creators. —Menlor Graphics*

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Virtual Prototype Creation A virtual prototype is a stand-alone executable derived from a TLM platform. Virtual prototypes are created either by using the virtual prototype dialog in the Vista GUI or by using the vistacreatevp command. Vista allows users to define the Vista parameters file, which contains the parameters of the design that can be modified during runtime (without recreating the executable). Users can also set the values of the default runtime environment variables used during virtual prototype simulation and copy additional directories and files into the virtual prototype...

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mode simulation speed is in the range of hundreds of MIPS, equal or close to real-time speed. In performance mode, the virtual prototype uses an approximately timed abstraction level in which transactions represent the phases of data transfer in a specific bus protocol (for example the address and data phases of an AHB read or write). The increased accuracy of performance mode does cause the virtual prototype to simulate at about two orders of magnitude slower than functional mode. Vista also supports higher levels of timing accuracy and performance using the Accuracy-Tunable functional...

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in analysis agents: a library of popular and intuitive system analysis and visualization tools that address the most common views desired by software engineers for evaluating the impact of their software and CPU/core operation on the final product functionality, performance, and power. Sourcery Analyzer agents enable users to view CPU states and statistics, file system activity over time, function calls and statistics, latency caps, lock wait and hold times, and process and thread states. CodeBench Virtual Edition also contains built-in VP software analysis agents the enable viewing: • VP...

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