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Tessent IJTAG

Tessent IJTAG
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Automation of the IEEE 1687 Standard Automation Support for the IEEE 1687 Standard Designing a modern product requires the integration of multiple IP blocks from both in-house and third party sources. The Mentor Graphics Tessent® IJTAG solution delivers comprehensive automation support for implementing the IEEE 1687 standard, providing plug-and-play IP test and instrumentation integration. Tessent IJTAG can be used by IP providers to ensure compliance to the standard as well as by chip designers to efficiently integrate IEEE 1687 compliant IP from various sources into their designs. These capabilities are critical to support the growing amount of IP used in today's large SoCs. IEEE 1687 Standard Overview The IEEE 1687 standard creates an environment for plug-and-play integration and use of the instrumentation portions of IP blocks. Instrumentation includes test, debug, and monitoring functions within the IP. The standard defines hardware rules related to the instrumentation interfaces and connectivity between these interfaces, a language to describe these interfaces and connectivity (Instrument Connectivity Language, or ICL), and a language to define operations to be applied to individual IP blocks (Procedural Description Language, or PDL). IEEE 1687 Certification for IP Supporting the IEEE 1687 standard provides several benefits to IP providers. It makes their products easier to integrate and hence more attractive to a wider customer base. It also provides improved testing and debugging capabilities and an overall more robust product. Tessent IJTAG lets IP providers verify that their IP is compliant to the IEEE 1687 standard. IP developers must create ICL that describes the IP in isolation, and PDL routines that describe usage of the IP. Tessent IJTAG can be used to create simulation testbenches that verify the ICL against the IP's Verilog description. It can also convert PDL routines into Verilog Silicon Test and Yield Analysis DATASHEET FEATURES: • Finds and extracts IJTAG ICL network data from gate-level or RTL netlist • Flexible IEEE 1687 network creation and insertion • Provides access to IEEE 1687 data structures, attributes and parameters • Retargets PDL commands from IP boundary to any point within an ICL-described IEEE 1687 network • Generates Verilog testbenches for PDL verification • Translates chip-level PDL patterns to ATE pattern formats (STIL, WGL) • Includes advanced introspection and design editing capabilities through Tessent Shell • BENEFITS: • Enables uniform access and use of embedded IP independent of the IP source • Expands available embedded IP choices • Reduces design schedules by accelerating integration of IEEE 1687 compliant IP • Achieves minimum cycle count for accessing IP within a reconfigurable network • Provides a common integration flow and access network for Tessent IP and any 3rd party IEEE 1687 compliant IP • Mentor Graphics award-winning Consulting Services available for maximum success —Menlor Graphics’

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for verification against the IP's ICL description using automatically generated simulation testbenches. IP Integration and Usage For the designer, IEEE 1687 enables robust integration and validation of various IP blocks into a larger design. It also provides several other benefits including activation of BIST (Built-In Self-Test) functionality and the observation of the test results, retargeting of IP-level control and access patterns to the top level of the chip, and on-the-fly test plan modification, with serial or parallel test execution of different IPs as needed. Successful application...

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