ANALOG/MIXED-SIGNAL (AMS) DESIGN AND VERIFICATION FEATURES AND BENEFITS: ■ Handles your most complex, full-custom IC schematic capture ■ Integration with SPICE simulation allowing waveform cross-probing and direct viewing of operating point simulation results in the schematic ■ Export formats: SPICE, EDIF, Verilog and VHDL ■ Import formats: OpenAccess, EDIF with automatic conversion of Mentor, Cadence, Laker and ViewDraw EDIF schematics, SPICE and Verilog ■ Cross-probe between schematic, layout and LVS report with net/ device highlighting ■ Configurable schematic Electrical Rule Checks (ERC) ■ Multiple-views per cell including: SPICE, schematic, Verilog, Verilog-A and Verilog-AMS views ■ Advanced array and bus support ■ Integrated with Tanner L-Edit Schematic Driven Layout (SDL) module to speed the layout and ECO process ■ Multiple library support with integrated library browser ■ Fully scriptable and expandable using TCL/Tk command language ■ Offers easy interoperability with third-party tools and legacy data Tanner S-Edit Schematic capture design and simulation cockpit shows schematics, simulation waveforms, model parameters, and simulation settings; the tool is easy to use and has the power to handle complex mixed-signal IC design capture. A Complete IC Design Capture Environment Tanner S-Edit is an easy-to-use design environment for schematic capture and design entry. It gives you the power you need to handle your most complex mixed-signal IC design capture. S-Edit is tightly integrated with Tanner T-Spice simulation, the Tanner L-Edit IC layout tool and the Tanner Verify DRC and LVS tool. S-Edit helps you meet the demands of today's fast-paced market by optimizing your productivity and speeding your concepts to silicon. A faster design cycle gives you more flexibility in moving to an optimal solution, freeing up more time and resources for process corner validation. The results are less risk downstream, higher yield and quicker time to market. Schematic Capture for the Most Complex Mixed-Signal IC Design ■ Bus support speeds the creation of mixed-signal designs ■ Advanced array support enables easy creation and editing of memory, imaging, or circuits with repetitive blocks ■ Rubberband connectivity editing with snap to pin (hotspots) enables faster design modifications ■ S-Edit displays evaluated parameters in real time over the course of the ■ Platform independence on design process; parameters with formulas based on other circuit parameters Windows or Linux can be displayed or evaluated ■ Ease of use: intuitive and quick ■ Auto symbol generation enables you to easily create symbols from learning curve schematics and synchronize any changes . Unparalleled customer support ■ All actions are fully scriptable through the TCL/Tk command language ■ Flexible licensing ■ Recordable scripts enable you to automate tasks or expand the tool for application-specific needs

■ Replayable logs permit recovery if there is an unexpected network or hardware failure ■ S-Edit performs net highlighting and keeps the net highlighted as you move through the hierarchy ■ Cross-probe between schematic, layout, and LVS report to highlight nets or devices ■ Schematic ERC enables you to check your design for common errors such as undriven nets, unconnected pins and nets driven by multiple outputs; the design checks are fully configurable, including custom validation scripts Tight Integration with Simulation ■ Drive the simulator from within the schematic capture environment. This...