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Olympus-SoC

Olympus-SoC
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Olympus-SoCd a t a s h e e t Mode, Corners, PST MT & Advanced Distributed Low-Power 5- 'S Olympus-SoC P&R System Floorplanning Physical Synthesis Routing (Litho, SI) Chip Assembly Chip Finishing/ECO Scalable Data Model Olympus-SoC is a comprehensive netlist-to-GDSII physical design implementation platform. Solving Advanced Design Challenges The Olympus-SoC™ Netlist-to-GDSII system comprehensively addresses the performance, capacity, time-to-market, power, and variability challenges. Olympus-SoC is a complete physical design implementation tool with best-inclass physical implementation engines including design planning, placement, physical synthesis, clock tree synthesis, routing, power optimization, manufacturability and a native sign-off quality timer with patented virtual timing graph technology. Olympus-SoC provides the highest capacity in the industry with a very compact and scalable database to handle designs that contain hundreds of millions of instances. The low power suite enables both leakage and dynamic power reduction throughout the flow and power-aware clock tree synthesis. Olympus-SoC also offers multi-threaded and distributed analysis and optimization throughout the flow to significantly reduce design cycle time. Native integration with Calibre minimizes physical verification ECOs and enables signoff checks during implementation. BENEFITS: ■ Optimal performance, power and area with true and concurrent optimization throughout the flow ■ Flexible architecture to support complex mulit-VDD design styles including MTCMOS and DVFS ■ Compact and scalable database provides highest capacity in the industry to effectively handle growing design sizes ■ Minimizes design planning iterations with data flow graph driven Automatic Macro Placement ■ Speed time-to-market with fewer design iterations and a suite of scalable parallelization technologies ■ Best area and highest utilization with proprietary area recovery technologies throughout the flow ■ Highest performance with patented multi-corner, multi-mode (MCMM) analysis and optimization architecture ■ Integrated Calibre signoff to achieve manufacturing closure during physical design implementation Flexible Routing Architecture Olympus-SoC features a scalable and flexible routing architecture that integrates the global, track, and detailed routing engines best suited to handle complex DRC and DFM requirements for all the technology nodes of the leading foundries. The Olympus-SoC router is able to address the increased number and complexity of DRC rules with fast runtimes and no loss in accuracy by performing a comprehensive and detailed analysis of the design rules and —Menlor Graphics’

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minimizing the number of operations that the router has to perform to ensure fast runtime without loss in accuracy. The unified Global Router based congestion modeling ensures excellent correlation in all stages of the design flow. The routing engine incorporates signoff-quality, variation-aware timing and optimization engine for SIand timing-driven routing. The router is highly flexible, with support for both gridded and non-gridded models and the use of a universal connectivity model for a friendly ECO flow. It also supports sophisticated non-default rules (NDRs) and all the DFM...

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Olympus-SoC reduces area with technologies like the unified global router-based congestion modeling, intelligent white space management, smart MP fixing for nested and interdependent cycles, Fin grid-aware placement, Vt- and implant-aware spacing and concurrent SI and MP fixing. Other area reduction technologies used throughout the flow include proprietary density management, dynamic area recovery, and congestion mitigation through clock tree synthesis (CTS) and post-CTS optimization. Highest Performance Leading-edge designs need to be analyzed and optimized for various design contexts and...

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Olympus-SoC also provides concurrent multi-Vt optimization, power gating, retention flop synthesis, support for gas station methodology, and power-aware buffering and sizing. Power-aware CTS minimizes power in the clock network with smart clock gate placement, slew shaping, clock gate cloning/de-cloning, register clumping and concurrent MCMM optimization, which ensures a balanced clock tree with optimal power. Premier Chip Assembly Flow Olympus-SoC allows designers to read in all the partitions of a large, complex design without any timing or physical abstractions, and to optimize the top...

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- Dynamic area recovery throughout the flow - Proprietary density management ■ TAT Reduction - Distributed and multithreaded analysis and optimization - Signoff physical verification during implementation with Calibre InRoute - Minimal ECO iterations through MCMM optimization - Signoff quality built-in timing and extraction engines - Industry's first multi-threaded timing engine ■ Highest Capacity - Compact database and flexible architecture - Ability to handle 100+ million instance designs - Flexible abstraction capabilities including SI-ILM, HTP, and black boxes - Unique synchronized...

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