D A T A S H E E T FEATURES AND BENEFITS: • Physically-aware RTL synthesis based on patented “PlaceFirst” technology • Optimization at RTL level for the best quality of results • Higher level of abstraction to handle 100+ million gates • Runtimes up to 10x faster than traditional RTL synthesis • Integrated cockpit for advanced cross probing between logical, physical, timing and other views Oasys-RTL addresses the need for higher capacity, faster runtimes, improved QoR, and physical awareness by optimizing at a higher level of abstraction along with offering an integrated floorplanning and placement capabilities. Overview The Oasys-RTL™ physical RTL synthesis solution is a revolutionary advancement in the state-of-the-art synthesis technology. It addresses the limitations of traditional RTL synthesis tools that were designed decades ago. Oasys-RTL has been architected to meet the needs of complex, advancednode, high performance designs with the capacity to handle 100+ million gates and up to 10X shorter runtimes. Oasys-RTL integrates full chip-level physical synthesis, floorplanning, and optimization at a higher level to enable RTL designers to accurately identify and resolve timing, routability, and power issues early in the design cycle. Oasys-RTL’s patented “PlaceFirst” synthesis technology enables optimization at the RTL level and delivers the best quality of results (QoR). Best Quality of Results Oasys-RTL’s patented “PlaceFirst” technology integrates placement into the core synthesis algorithms as a primary cost function, thereby enabling high-level optimization similar to what modern compilers can do to software programs. Oasys-RTL’s physical RTL synthesis works by partitioning the RTL into virtual placeable entities, and then refining those down into actual library cells so that there is always a full placement that goes with the timing values. In addition, Oasys-RTLworks with the full-chip global view of the design, and the effects of any physical changes are immediately propagated to the entire design to drive subsequent synthesis runs. This leads to reliable convergence and superior QoR. Oasys-RTL applies cutting edge global placement technologies in combination with • Industry’s Only RTL-level floorplanning capabilities for faster floorplan closure • Integrated links for formal equivalency checking • Parallel design space exploration of PPA metrics • Comprehensive power o

global routing connectivity and congestion-aware algorithms to minimize congestion related to timing closure. Oasys-RTL is thus able to deliver the QoR by addressing the limitation of the traditional synthesis tools that focus on very low, gate-level local optimizations that limit the QoR improvement opportunities or take a large number of small incremental computations to achieve acceptable results. Highest Capacity and Fastest Runtime Oasys-RTL has the ability to handle 100+ million gate designs with up to 10x faster runtime compared to traditional synthesis tools. The significant improvements...

and congestion issues and resolve the problems early in the design cycle. Oasys-RTL is the first tool to provide all the design views, from logical to physical to timing, in a single RTL synthesis platform. Visualize and interact with the physical results of RTL synthesis. Crossprobing allows designers to make changes and re-run synthesis quickly. Oasys-RTL also provides different physical views for early debug including static/dynamic power map, congestion map, critical timing map, and hierarchical floorplanning view. Design Space Exploration The capacity and speed of Oasys-RTL enables designers...