LeonardoSpectrum with LeonardoInsight Major product features: • One tool, one learning curve, one set of scripts, for CPLDs, FPGAs, or ASICs • Mix VHDL, Verilog, and EDIF to enable design reuse and instantiation of intellectual property • Highest QoR with the speed and features you need for large designs • HDLInventor™ creates optimized HDL code fast and facilitates company wide sharing of intellectual property • Technology-specific F.A.S.T. Optimization ensures a fast and small design • P&R Integrator simplifies place-and-route and delivers improved results • Built-in partitioning speeds ASIC prototyping and verification process Proprietary ease-of-use features such as FlowTabs™ and QuickSetup enable first time FPGA synthesis. Enhance Productivity with LeonardoSpectrum LeonardoSpectrum™ combines push-button ease of use with the powerful control and optimization features associated with workstation-based ASIC tools. LeonardoSpectrum allows you to create CPLDs, FPGAs, or ASICs in VHDL or Verilog within one synthesis environment. For design and analysis, set up is a snap, and you won't find a more flexible tool for design and analysis. A proven best-in-class solution, LeonardoSpectrum also provides synthesis horsepower for the FPGA Advantage™ flow from Mentor Graphics. Users faced with design challenges can access advanced synthesis controls within the exclusive LeonardoSpectrum FlowTabs and PowerTabs™. In addition, the powerful debugging features and exclusive five-way cross-probing in LeonardoInsight™ accelerate your analysis of synthesis results. Power Combined with Ease of Use If desired, you can perform 100 percent push-button synthesis using LeonardoSpectrum. But users faced with complex designs can access advanced synthesis controls within LeonardoSpectrum’s exclusive PowerTabs, which provide users with the flexibility and control to target a design to meet the speed or area req

True Hierarchical Support for Incremental Synthesis Hierarchical design enables you to perform incremental design and team design. You can modify individual modules at the RTL level, then re-synthesize and re-optimize while preserving netlist information in surrounding blocks. This significantly reduces compile times on complex, multi-block designs. An incremental approach is also supported during synthesis. Constraints can be “tightened” on sub-blocks and re-optimized to fine tune timing or area goals following place and route operations. Blocklevel design provides the key to efficient interaction...

Partitioning LeonardoSpectrum makes it easy to partition designs for prototyping purposes. It’s often desirable to prototype a large FPGA or ASIC in multiple, smaller FPGAs. True hierarchical support makes it easy to group and ungroup design elements, which can then be targeted for single or multiple chips. LeonardoSpectrum is the only synthesis tool that offers a truly seamless, technology-neutral environment, from FPGAs to ASICs. This allows retargeting circuits: • When acquiring or re-using IP • When retargeting FPGA code to an ASIC device • When a decision is made to retarget to a new device...

HDL Source Code Viewer Understanding how synthesis results and HDL source constructs relate to one another is crucial in determining coding styles. Even small changes can improve designs by 30–40 percent or more. Further productivity increases are available using the HDL viewer’s tight integration with HDLInventor for technology-specific template selection. RTL Block-based Schematic Viewer You need insight into what your HDL code produces to find the best design alternatives early in the design cycle. LeonardoInsight automatically creates a block-based schematic from the RTL code before the synthesis...