Results Viewing Environment Physical Verification D A T A S H E E T FEATURES AND BENEFITS: ■■ Universal integration with layout environments: Using the Calibre RVE interface minimizes training and support overhead, and provides a single, consistent interface across all your design tools. ■■ Fast debugging time for cell, block and full-chip designs: Whether you have 10 or 106 errors, the Calibre RVE interface provides fast response time with minimal memory overhead Calibre RVE’s robust viewing and debugging capabilities connect results from all Calibre tools back into your schematic or layout viewing environments for quick design closure. Calibre RVE Results Viewing Environment: Accelerating Time to Tapeout While the Calibre® platform’s best-in-class engines provide physical and circuit verification results in record time, you still need to fix the identified layout issues before you can tape out. The Calibre RVE™ results viewing environment provides fast, flexible, and easy-to-use graphical debugging capabilities that minimize your turnaround time and get you to “tapeout-clean” on schedule. The Calibre RVE interface is integrated into all popular layout environments, including the Mentor® Pyxis® design environment, the Mentor Tanner design tool suite, the Calibre DESIGNrev™ chip finishing platform, Synopsys® IC Compiler, Synopsys IC Compiler II, Cadence® SOC Encounter®, Cadence Innovus®, Cadence Virtuoso®, Synopsys Laker™, Seiko, and Keysight. Whatever design environment you use, the Calibre RVE interface provides the debugging technology you need for fast, accurate error resolution. Physical Verification However complex the rule deck, the Calibre RVE interface can handle it. Even with millions of error results, the Calibre RVE environment provides fast navigation through the layout, while its filtering capability allows you to focus on analyzing and fixing critical errors first. The tabbed viewing format enables you to easily organize data by tiling the display windows side by side. And, because the Calibre RVE interface is designed with a low-memory footprint, you can run it on the same machine you use for your design environment. ■■ Single platform for all Calibre results: The Calibre RVE interface provides results debugging across the entire Calibre product line, giving you a single interface to learn and support for all your Calibre tools. ■■ Reliability: With thousands of users worldwide, the Calibre RVE interface sets the standard for debug reliability and accuracy. ■■ Schematics: Visualizing the intended connectivity of the source schematic against the connectivity realized in the layout greatly speeds resolution of LVS errors. ■■ Short isolation: Identifying a short and quickly verifying a virtual fix interactively signi

The Calibre RVE interface physical verification capabilities include: ■■ Automatic display of DRC check-relevant layers in the design environment using the check text override (CTO) file during results highlighting eliminates the need to manually turn on/off design layers, speeding up the DRC debug process ■■ Filtering capability eliminates clutter and lets designers perform focused debugging ■■ Interactive results waiving, waiver criteria specification, and waiver export for DRC results provides designers with a full view of all waivers ■■ Interactive HTML report generation eliminates tedious...

■ Advanced short isolation function that can be run hierarchically and by layer to quickly isolate the root cause of a texted short. When the short isolation algorithm is unable to pinpoint the short, the Calibre RVE interface enables the user to interactively walk through the shorted-path, isolate the issue, make a virtual fix and confirm the validity of the fix without repeating the batch Calibre LVS run. Parasitic Extraction Accurate timing and performance simulations for leading edge circuit designs depend on accurate parasitic extraction. Using the Calibre xRC™ and Calibre xACT™ extraction...