HG010WZ003
50Pages

Catalog excerpts

SPECIFICATION FOR TFT LCD MODULE CUSTOMER: CUSTOMER MODULE :_ □Preliminary Specification ■Final Specification Customer Confirmation column: Approved by :Dept. :Data : Please return one of the copies of the specification with your signature to us within two weeks after you receive this document.If it is not returned,we will assume that you agree to the entire contents of this specification document.

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深圳市鸿光显示有限公司 1. WARRANTY Supplier warrants that the products delivered pursuant to this specification (or order) will conform to the agreed specifications for twelve (12) months from the shipping date ("Warranty Period"). Supplier is obligated to repair or replace the products which are found to be defective or inconsistent with the specifications during the Warranty Period without charge, on condition that the products are stored in the original packages at 25°C±5°C, 55%±10%RH or used as the conditions specified in the specifications. Nevertheless, Supplier is not obligated to repair or...

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深圳市鸿光显示有限公司 3. MECHANICAL DATA NO Aperture Rate Active Area Panel Size Module Size * Panel thickness includes substrate glass, cover glass and UV glue thickness.

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5.2 ELECTRO-OPTICAL CHARACTERISTICS PANEL ELECTRICAL SPECIFICATIONS (1) Normal mode condition: (Charge Pump) - VBAT = 3.6V - Contrast setting : 0XB0 - Charge Pump Setting:0x14 - Frame rate : 105Hz - Duty setting : 1/64 (2) Sleep mode condition: When send 0xae command OLED display off and memory data will be maintained. (3) Wake up condition: When send 0xaf command OLED will be turned on.

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Note: (A) Under VBAT = 3.6V (Charge Pump), Ta = 25°C, 50% RH. (B) Life time is defined the amount of time when the luminance has decayed to less than 50% of the initial measured luminance. (1) Setting of 90cd/m2 : (Charge Pump) - Contrast setting : 0Xb0 - Charge Pump Setting:0x14 - Frame rate : 105Hz - Duty setting : 1/64

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深圳市鸿光显示有限公司 7. INTERFACE 7.1 FUNCTION BLOCK DIAGRAM 7.2 PANEL LAYOUT DIAGRAM

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7.4 GRAPHIC DISPLAY DATA RAM ADDRESS MAP The GDDRAM is a bit mapped static RAM holding the bit pattern to be displayed. The size of the RAM is 128 x 64 bits and the RAM is divided into eight pages, from PAGE0 to PAGE7, which are used for monochrome 128x64 dot matrix display, as shown in below figures. GDDRAM pane' structure When one data byte is written into GDDRAM, all the rows image data of the same page of the current column are filled (i.e. the whole column (8 bits) pointed by the column address pointer is filled.). Data bit D0 is written into the top row, while data bit D7 is written...

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7.5 INTERFACE TIMING CHART 7.5.1 4-Wire Serial Interface Timing Characteristics

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7.5.2 3-Wire Serial Interface Timing Characteristics

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7.5.3 IIC Serial Interface Timing Characteristics Conditions: V’dd * V&s =VDD - V’ss - 1.65V to 3.3 V i'a : PC' Interface Timing Characteristics l2C interface Timing characteristics y^::z:::xjrx kcrno

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8. POWER ON / OFF SEQUENCE & APPLICATION CIRCUIT8.1 POWER ON / OFF SEQUENCE Power ON sequence: 2. Wait for toN- Power ON Vbat.(1) (where Minimum tow = Oms) 3. After Vdd become stable, wait at least 20ms (to), set RES# pin LOW (logic low) for at least 3us (ti)l3land then HIGH (logic high). 4. After set RES# pin LOW (logic low), wait for at least 3us(tj).Then input commands with below sequence: a. 8Dh for enabling internal charge pump b. AFh for display ON 5. SEG/COM will be ON after 100ms (W). Note: (1 )Vbat should be kept float (i.e. disable) when it is OFF. (2)Power Pins (Vbat) can never...

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深圳市鸿光显示有限公司 8.2 APPLICATION CIRCUIT 8.2.1 This circuit is for 4 wire SPI interface, Charge pump application. Note: Vbat is also can be set 3.3V and connect VDD together. For charge pump mode, VCC not need to connect external voltage supplier.

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深圳市鸿光显示有限公司 8.2.2 This circuit is for 3 wire SPI interface, Charge pump application. Note: Vbat is also can be set 3.3V and connect VDD together. For charge pump mode, VCC not need to connect external voltage supplier.

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深圳市鸿光显示有限公司 8.2.3 This circuit is for IIC interface, Charge pump application. Recommended components： C5、C6：4.7uF/25V(Tantalum type) or VISHAY (572D475X0025A2T) C3、C4：1uF/16V(0603) C1、C2：1uF/16V(0603) R2、R3：10K(0603) (Should be adjusted based on IIC waveform) R1：620Kohm 1%(0603) Note: Vbat is also can be set 3.3V and connect VDD together. For charge pump mode, VCC not need to connect external voltage supplier.

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深圳市鸿光显示有限公司 8.3 Initial code void Initial_ic(void) { Write_Command(0xAE); //Display Off Write_Command(0xD5); //SET DISPLAY CLOCK Write_Command(0x90); //105HZ Write_Command(0xA8); //Select Multiplex Ratio Write_Command(0x3F); //Default => 0x3F (1/64 Duty) Write_Command(0xD3); //Setting Display Offset Write_Command(0x00); //00H Reset Write_Command(0x40); //Set Display Start Line Write_Command(0x8D); //Set Charge Pump //Write_Command(0x10); //Disable Charge Pump Write_command(0x14); //Enable Charge Pump Write_command(0xAD); // Internal IREF Setting Write_command(0x20); // Disable internal IREF...

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深圳市鸿光显示有限公司 Write_Command(0x30); Write_Command(0xA4); //Entire Display ON Write_Command(0xA6); //Set Normal Display Clear_Ram(); Write_Command(0xAF); //Display ON } void Clear_Ram (void) { int i,j; for(i=0;i<8;i++) { Write_Command (0xb0+i); //Set Page Write_Command (0x00); //Lower Column Address Write_Command (0x10); //Higher Column Address for(j=0;j<128;j++) { data_out(0x00); } } 8.4 COMMAND TABLE Refer to IC Spec.: SSD1315

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9. RELIABILITY TEST CONDITIONS No. Test and measurement conditions 1. All measurements shall not be started until the specimens attain to temperature stability. 2. The degradation of Polarizer are ignored for item 1,3 & 5. Evaluation criteria 1. The function test is OK. 2. No observable defects. 3. Luminance: > 50% of initial value. 4. Current consumption: within ± 50% of initial value.

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深圳市鸿光显示有限公司 11. PACKING SPECIFICATION Item Holding Trays Total Trays per Primary Box (Including 1 Empty Tray) per Carton (4 as Major / Maximum)

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12. OUTGOING INSPECTION PROVISION 1. / SAMPLING METHOD MIL-STD-1916 / inspection level III / normal inspection / single sample inspection (2) LevelUbOM Level II Major Level III; Minor Level II

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