Version: 1.2 Release Date: 2024-09-27 Shenzhen Goodix Technology Co., Ltd.
Open the catalog to page 1GODDiX Contents GR5526 Copyright © 2024 Shenzhen Goodix Technology Co., Ltd. DS-GR5-00030-EN
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Open the catalog to page 7GODDiX Contents GR5526 Copyright © 2024 Shenzhen Goodix Technology Co., Ltd. DS-GR5-00030-EN Product Datasheet Rev. 1.2 (2024-09-27) VIII
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Open the catalog to page 29The Goodix GR5526 family is a single-mode, low-power Bluetooth 5.3 System-on-Chip (SoC). It can be configured as a Broadcaster, an Observer, a Central, and a Peripheral and supports the combination of all the above roles, making it an ideal choice for Internet of Things (IoT) and smart wearable devices. In addition, it supports Bluetooth Low Energy (Bluetooth LE) direction finding: angle of arrival (AoA) and angle of departure (AoD), as well as LE Audio, made possible by LE Isochronous Channels. Based on ARM Cortex -M4F CPU core, the GR5526 series integrates Bluetooth 5.3 Protocol Stack, a 2.4...
Open the catalog to page 30ARM Cortex -M4F 32-bit micro-processor with floating point support ◦ Built-in Memory Protection Unit (MPU) supporting eight programmable regions ◦ Hardware Floating Point Unit (FPU) ◦ Built-in Nested Vectored Interrupt Controller (NVIC) ◦ Non-maskable Interrupt (NMI) input ◦ Serial Wire Debug (SWD) with 16 breakpoints, two watchpoints, and a debug timestamp counter ◦ 51 ^A/MHz execution from Flash @ 3.3 V, 96 MHz • On-chip memory ◦ 512 KB data SRAM with retention capabilities ◦ 8 KB cache SRAM with retention capabilities ◦ Stack ROM (including boot ROM and Bluetooth LE Stack) ◦ 1 MB internal...
Open the catalog to page 31◦ 2.5D GPU for graphics acceleration (for GR5526VGBIP and GR5526RGNIP only) ◦ 1 x Dual-lane SPI (DSPI) interface for display, with Mobile Industry Processor Interface (MIPI) Display Bus Interface (DBI) Type-C support ◦ 3 x Quad SPI (QSPI) interfaces, up to 48 MHz; supporting direct access via memory mapping when connecting with external NOR Flash ◦ Display Controller (DC) module with MIPI DBI Type-C support and 2D graphics blending integrated (for GR5526VGBIP and GR5526RGNIP only) ◦ Complete secure computing engine: - Hash-based Message Authentication Code (HMAC-SHA256) - True random number generator...
Open the catalog to page 32◦ On-chip DC-DC to provide RF Analog voltage and supply core LDO ◦ On-chip I/O LDO to provide I/O voltage and supply external components, maximum I/O LDO drive strength: 30 mA ◦ Programmable thresholds for brownout detection (BOD) • Low-power consumption modes ◦ Sleep mode: 3.3 ^A (Typical) at 3.3 V VBAT input with 128 KB SRAM retention on and LFXO_32K off; woken up by 8 sources of always-on domain ◦ Ultra deep sleep mode: 2.4 ^A (Typical); internal power (all SRAM included) and LFXO_32K removed from entire chip except always-on domain; woken up by Sleep Timer and AON GPIOs ◦ OFF mode: 200 nA...
Open the catalog to page 33Active Mode Voltage Sensor Temperature Sensor Idle Mode Deep Sleep Mode Ultra Deep Sleep Mode Figure 1-1 GR5526 block diagram • Bluetooth subsystem ◦ A 2.4 GHz transceiver and a digital communication core that supports Bluetooth 5.3 An ARM Cortex -M4F with all the required memories and peripherals ◦ Security cores that can be used for application security and secure boot implementation ◦ GPU + DC to enhance processing capabilities • Power management unit (PMU) subsystem ◦ All the required power management modules to supply sufficient power for both internal modules and external peripherals ◦...
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