RTH020 12 GHz Bandwidth 1 GS/s Dual Track-and-Hold Features ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ 12 GHz Input Bandwidth (0.25 Vpp VIN Differential) 100 - 1000 MHz Sampling Rate (TH1) 100 - 1000 MHz Output Data Rate (TH2) -76 dB Hold Mode Distortion (1.0 GHz 0.25 Vpp VIN Differential) -46 dB Hold Mode Distortion (1.0 GHz 0.25 Vpp VIN SE) -53 dB Hold Mode Distortion (4.0 GHz 0.25 Vpp VIN Differential) -36 dB Hold Mode Distortion (4.0 GHz 0.25 Vpp VIN SE) < 50 fs Aperture Jitter < 250 ps Acquisition Time < 50 ps Rise Time (20 - 80%) Differential Analog Input/Output Output Held more than Half Clock Cycle Track Mode Select Figure 1. Functional Block Diagram Product Description RTH020’s bandwidth and aperture jitter enable 1 GS/s accurate sampling of DC to multi-GHz signals. The differential-to-differential dual trackand-hold cascades two track-and-hold circuits, TH1 and TH2. The RTH020 provides a held output for more than half a clock cycle, easing bandwidth requirements of subsequent circuitry relative to the case of a single track-and-hold (TH). The option to independently clock TH1 and TH2 further relaxes this requirement for subsampling applications. Ordering information PART NUMBER RTH020-HD RTH020-DI EVRTH020-HD DESCRIPTION 13 Lead HSD Package Die Evaluation Board with a RTH020-HD Teledyne Scientific Company reserves the right to make changes to its product specifications at any time without notice. The information furnished herein is believed to be accurate; however, no responsibility is assumed for its use.

Output Voltages Vterm (Output Termination Voltage) to GND.. -2.5 to +0.5V Temperature Case Temperature …………..……………… -15 to +85 °C Junction Temperature .………………………..….. +125 °C Lead, Soldering (10 Seconds) .………………….. +220 °C Storage ….…………………………………… -40 to 125 °C Teledyne Scientific Company reserves the right to make changes to its product specifications at any time without notice. The information furnished herein is believed to be accurate; however, no responsibility is assumed for its use.

DC Electrical Specification Test Conditions (see notes for specific conditions): Room Temperature; VCC = 5V; VEE = -5.2V; Clocks: 1GHz, 0.6Vpp Differential; Input: 250mV Single-Ended; Outputs Terminated Into 50 Ω to 0V. PARAMETER DC TRANSFER FUNCTION Gain Offset Voltage Common-Mode Rejection CONDITIONS, NOTE Absolute Value 0.25 Vpp at INP and INN, in phase TEMPERATURE DRIFT Warm-up Time After Power-up ANALOG INPUT (INP, INN) Input Resistance RIIN Each Lead to GND Input Capacitance CIIN Each Lead to GND CLOCK INPUTS (CLK1P, CLK1N, CLK2P, CLK2N) Input Resistance RCIN Each Lead to GND Input Capacitance...

CONDITIONS, NOTE DYNAMIC TRACK MODE PERFORMANCE, SINEWAVE INPUT -3dB Gain, TH1 & TH2 In Track Track Bandwidth 1000 MHz Mode Gain Flatness Deviation ±0.5 dB Integrated Noise Input Referred 400 μV Noise Floor Input Referred 3.9 nV/√Hz DYNAMIC HOLD MODE PERFORMANCE, SINEWAVE INPUT Gain Flatness Deviation GFD From DC to 6GHz ±1 dB Integrated Noise Input Referred 550 μV Noise Floor Input Referred 5.3 nV/√Hz DYNAMIC HOLD MODE PERFORMANCE, SINEWAVE INPUT, 0.25Vpp DIFFERENTIAL Bandwidth BWL -3dB Gain, 0.25 VPP Differential 11 12 GHz SFDR 60 MHz SFDR1 0.25 Vpp Differential Input 65 80 dB SFDR 1060 MHz...

CONDITIONS, NOTE DYNAMIC HOLD MODE PERFORMANCE, SINEWAVE INPUT, 0.5Vpp DIFFERENTIAL Bandwidth BWM -3dB Gain, 0.5 VPP Differential 10 10 SFDR 60 MHz SFDR14 0.5 Vpp Differential Input 65 76 SFDR 1060 MHz SFDR15 0.5 Vpp Differential Input 62 72 SFDR 2060 MHz SFDR16 0.5 Vpp Differential Input 55 58 SFDR 3060 MHz SFDR17 0.5 Vpp Differential Input 51 53 SFDR 4060 MHz SFDR18 0.5 Vpp Differential Input 46 49 SFDR 5060 MHz SFDR19 0.5 Vpp Differential Input 38 46 SFDR 6060 MHz SFDR20 0.5 Vpp Differential Input 37 43 SFDR 7060 MHz SFDR21 0.5 Vpp Differential Input 38 40 SFDR 8060 MHz SFDR22 0.5 Vpp Differential...

CONDITIONS, NOTE TRACK TO HOLD SWITCHING AND HOLD STATE, TH1 After V(CLK1P) - V(CLK1N) Goes Aperture Delay ta Neg. 1,2 Aperture Jitter Jitter Free 1-GHz 0.5-Vpp CLK1 Δt At Hold Capacitors. ttrack1,min Settling Time to 1 mV ts Observed 3 Differential Pedestal/VIN Diff. Droop Rate/VIN 4 Hold Noise Per Sqrt (Hold Time) 5 Maximum Hold Time tHD1,MAX HOLD TO TRACK SWITCHING AND TRACK STATE, TH1 6 Acquisition Time to 1 mV tacq At Hold Caps, FSR Step At Input Max. Acq. Slew Rate Dvdt,max At Hold Caps, FSR Step At Input 20 – 80%, 0.5Vpp input, defined at Rise Time tr1 the sampling bridge. Minimum Track...

CONDITIONS, NOTE CLOCK INPUTS (CLK1P, CLK1N, CLK2P, CLK2N) 9 Amplitude VCPP Common Mode Voltage VCCM CLK1 Frequency FCLK1 CLK2 Frequency FCLK2 ANALOG INPUT (INP, INN) Full Scale Range FSR Common Mode Voltage VCM DIGITAL INPUT (TMS) Input High Voltage VIH Input Low Voltage VIL Open TMS ≈ –1.4V ANALOG OUTPUT (OUTP, OUTN) Ext. Termination Voltage VTERM Required From Outputs To Vterm Ext. Termination Resistor RTERM POWER SUPPLY REQUIREMENTS Positive Supply Voltage VCC Negative Supply Voltage VEE 10 OPERATING TEMPERATURE Case Temperature Tc Measured at Bottom Plate Junction Temperature Tj For > 500...

OUTP OUTN FUNCTION Power Supply Ground Positive Power Supply, +5.0V Negative Power Supply, -5.2V Clock 1 Input: High = TH1 in Track Mode Low = TH1 in Hold Mode Complementary Clock 1 Input Clock 2 Input: High = TH2 in Track Mode Low = TH2 in Hold Mode Complementary Clock 2 Input Analog Input Complementary Analog Input Track Mode Select: Open = Sampled operation Ground = TH1 and TH2 in Track Mode Analog Output Complementary Analog Output Figure 2. RTH020-HD pin configuration (top view, not to scale) 13 lead HSD Package. Teledyne Scientific Company reserves the right to make changes to its product...