RDA112M4MSLPD 12 Bit 2.0 GS/s Low Power Master-Slave Differential
14Pages

RDA112M4MSLPD DATASHEET DS_0098PA2-1309 Teledyne Scientific Company reserves the right to make changes to its product specifications at any time without notice. The information furnished herein is believed to be accurate; however, no responsibility is assumed for its use. Page 1 of 14 RDA112M4MSLPD 12 Bit 2.0 GS/s Low Power Master-Slave Differential 4:1 MUXDAC Features 12 Bit Resolution 2.0 GS/s Sampling Rate 4:1 or 2:1 Multiplexed Data Input LVDS Compatible Divided by 2, 4 or Divided by 8 Clock Out (DDR Support) Master-Slave Mode for Synchronous Operation (Multiple Devices) Differential Analog Output Adjustable Output Signal: Up to 600mV (single-ended) Offset Binary Input Code Format DNL: ±2 LSB Typical INL: ±2 LSB Typical 3.3V Power Supply, 2.5V for Input Signals 1.1W Power Dissipation Typical 224 Balls BGA Package Product Description The RDA112M4MSLPD is a low-power 12 bit digital to analog converter (DAC) with a data sampling rate of 2.0GS/s. It has been optimized for applications demanding a high performance low-power DAC, achieving more than 50 dBc of spurious free dynamic range (SFDR) at 2 GS/s with fout of 667 MHz. Interface to the DAC is made easy by its multiplexer (in 4:1 or 2:1 mode), allowing direct connection to a FPGA or ASIC with no extra components. The DAC utilizes a segmented current source to reduce glitch energy and achieve high linearity performance. For better dynamic performance, the DAC outputs are internally terminated with 50Ù resistors. It outputs a nominally 300mVpp signal when terminated with external 50Ù resistors. Ordering information PART NUMBER DESCRIPTION RDA112M4MSLPD-DI 12 BIT 2.0GS/s MUXDAC, DIE RDA112M4MSLPD-BG 12 BIT 2.0GS/s MUXDAC, BGA Package EVRDA112M4MSLPD-BG RDA112M4MSLPD-BG Evaluation Board Figure 1 - Functional Block Diagram

RDA112M4MSLPD DATASHEET DS_0098PA2-1309 Teledyne Scientific Company reserves the right to make changes to its product specifications at any time without notice. The information furnished herein is believed to be accurate; however, no responsibility is assumed for its use. Page 3 of 14 DC Electrical Specification Test Conditions (see notes for specific conditions): Room Temperature; VDDA = 3.3V; VDD33 = 3.3V; VDD25 = 2.5V; VDDIO = 2.5V; VTT = 1.3V; VREF = 1.2V; MSM = master; MXSEL = 4:1; RBS = 1K6Ù; Clock: 2GHz, 0.6Vpp Differential; Outputs Terminated into 50Ù to 3.3V. PARAMETER SYMBOL...

RDA112M4MSLPD DATASHEET DS_0098PA2-1309 Teledyne Scientific Company reserves the right to make changes to its product specifications at any time without notice. The information furnished herein is believed to be accurate; however, no responsibility is assumed for its use. Page 4 of 14 AC Electrical Specification Test Conditions (see notes for specific conditions): Room Temperature; VDDA = 3.3V; VDD33 = 3.3V; VDD25 = 2.5V; VDDIO = 2.5V; VTT = 1.3V; VREF = 1.2V; MSM = master; MXSEL = 4:1; RBS = 1K6Ù; Clock: 2GHz, 0.6Vpp Differential; Outputs Terminated into 50Ù to 3.3V. PARAMETER SYMBOL...

RDA112M4MSLPD DATASHEET DS_0098PA2-1309 Teledyne Scientific Company reserves the right to make changes to its product specifications at any time without notice. The information furnished herein is believed to be accurate; however, no responsibility is assumed for its use. Page 5 of 14 Operating Conditions PARAMETER SYMBOL CONDITIONS, NOTE MIN TYP MAX UNITS 13.0 HIGH CLOCK INPUT (HCLKIP, HCLKIN) 13.1 Amplitude VCPP,HCLKI 200 1000 mVpp 13.2 Common Mode Voltage VCCM,HCLKI 2000 2800 mV 13.3 Maximum Frequency FMAX,HCLKI 2000 MHz 13.4 Minimum Frequency FMIN,HCLKI 1 MHz 14.0 LOW CLOCK INPUT...

RDA112M4MSLPD DATASHEET DS_0098PA2-1309 Teledyne Scientific Company reserves the right to make changes to its product specifications at any time without notice. The information furnished herein is believed to be accurate; however, no responsibility is assumed for its use. Page 7 of 14 Pin Layout (TOP view) Figure 2 - RDA112M4MSLPD pinout. (top view)

RDA112M4MSLPD DATASHEET DS_0098PA2-1309 Teledyne Scientific Company reserves the right to make changes to its product specifications at any time without notice. The information furnished herein is believed to be accurate; however, no responsibility is assumed for its use. Page 8 of 14 Typical Operating Circuit Figure 3 - RDA112M4MSLPD typical operating circuit, single device, SDR output clock, using internal voltage reference.

RDA112M4MSLPD DATASHEET DS_0098PA2-1309 Teledyne Scientific Company reserves the right to make changes to its product specifications at any time without notice. The information furnished herein is believed to be accurate; however, no responsibility is assumed for its use. Page 9 of 14 Figure 4 - RDA112M4MSLPD typical operating circuit in master-slave configuration. Figure 5 - RDA112M4MSLPD placement in master-slave configuration.

RDA112M4MSLPD DATASHEET DS_0098PA2-1309 Teledyne Scientific Company reserves the right to make changes to its product specifications at any time without notice. The information furnished herein is believed to be accurate; however, no responsibility is assumed for its use. Page 10 of 14 Equivalent Circuit Figure 6 - RDA112M4MSLPD high speed clock input circuit (HCLKI), showing a single ended clock source. The clock common mode is set by VTT (which in an AC coupled clock configuration is 2V). Figure 7 - RDA112M4MSLPD low speed clock input (LCLKI) and data in input (DI) circuit.

RDA112M4MSLPD DATASHEET DS_0098PA2-1309 Teledyne Scientific Company reserves the right to make changes to its product specifications at any time without notice. The information furnished herein is believed to be accurate; however, no responsibility is assumed for its use. Page 11 of 14 Figure 8 - RDA112M4MSLPD low speed clock output (LCLKO) circuit. Figure 9 - RDA112M4MSLPD control input (CKSEL, DSEL<0:1>, MSM, MXSEL) circuit. Term is internally connected to GND except if the input is CLKSEL, in which case Term is connected to VDD25.

RDA112M4MSLPD DATASHEET DS_0098PA2-1309 Teledyne Scientific Company reserves the right to make changes to its product specifications at any time without notice. The information furnished herein is believed to be accurate; however, no responsibility is assumed for its use. Page 12 of 14 Figure 10 - RDA112M4MSLPD voltage reference circuit.