Product Overview
The RDA112RZ is a high-performance 12-bit digital-to-analog converter (DAC) with a sampling rate of 1.5 GS/s, suitable for applications requiring output signals over the 2nd Nyquist band. It offers a spurious free dynamic range (SFDR) of 60 dBc at 1.5 GS/s with an output frequency of 667 MHz. The DAC features a segmented current source to reduce glitch energy and improve linearity, along with a track and attenuate circuit for a consistent response in the 2nd Nyquist band.

Pin Description
The datasheet includes a detailed pin layout and description, covering power supply pins, test pins, clock inputs, digital inputs, and differential outputs.

Typical Operating Circuit
The DAC uses MSB segmentation for optimal linearity, with a master-slave flip-flop to minimize data skew. A track-and-attenuator circuit is integrated to enhance output bandwidth and reduce glitches. The DAC output follows the relationship VFS = 0.3xVREF, with an internal reference circuit providing approximately 20dB supply rejection.

Signal Description
Power supplies are isolated within the chip to separate digital and analog sections. The analog outputs should be connected through a 50 Ω resistor to GNDA for a full-scale amplitude of 0.6 volt. The VREF pin allows for an external voltage reference to override the internal reference for precise full-scale control.

Additional Specifications
The RDA112RZ DAC is designed with a reference voltage of -2.0 volts and an output resistance of 560 Ω ±10%. Proper bypass circuitry is required for digital reference pins.

Input Clock
The DAC can be driven by typical ECL circuits or a differential sinusoidal clock. The CLKP and CLKN inputs are internally terminated with 50Ω, and the VTT pin should be connected to a well-decoupled -2.0 volt supply. A low-jitter clock source is recommended to maintain the DAC's output phase noise within acceptable limits. For a 900MHz output, clock jitter should be less than 280fs for a 10-bit equivalent, 62dB SNR.

Data Input and DClock
Data inputs follow LVDS standards with 100 Ω terminations included on the chip. The DAC uses a four-clock deep FIFO for interfacing with digital driver chips, allowing a skew margin of 1.5 clock cycles. The RESET pin enables the read clock of the FIFO when low.

Package Information
The RDA112RZ is available in a 60-pin QFP package with a CuW base for heat spreading. The package body is electrically tied to GND internally, with dimensions provided in inches (mm).