Digital to Analog Converters (DAC) RDA012RZ

Product catalog summary

Product Overview
The RDA012RZ is a 12-bit Gallium Arsenide (GaAs) Digital-to-Analog Converter (DAC) designed for ultra-high-speed applications with a data update rate exceeding 1 Gsample/s. It features a segmented current source to minimize glitch energy and enhance linearity, and includes a track-and-attenuate circuit for flat response in the second Nyquist band.

Key Features

12-bit resolution with a minimum sampling rate of 1 GS/s and typical rate of 1.5 GS/s.
10-bit static linearity and LVDS compliant digital inputs.
Power supply requirements: -5.2V and +3.3V.
Output swing of 600 mV with 50 Ω termination.
Return-to-zero output for second Nyquist operation.
Fast settling time of less than 1 ns for specific code transitions.

Specifications
Absolute Maximum Ratings

Supply voltages range from -0.3V to +3.8V.
Operating temperature range from -40°C to +85°C.
Storage temperature range from -60°C to +125°C.

DC Electrical Specifications

Differential nonlinearity and integral nonlinearity both range from -0.1% to 0.1% FS.
Full-scale output swing is 1200 mVpp differentially and 600 mVpp single-ended.

AC Electrical Specifications

Spurious Free Dynamic Range (SFDR) is 50 dBc for various output frequencies.
Clock feedthrough is -40 dB.

Operating Conditions

Clock input amplitude ranges from 400 mV to 800 mV.
Maximum clock frequency is 1.5 GHz.
Power supply requirements include a positive supply of 3.3V and negative supplies of -5.2V for both analog and digital sections.

Pin Description
The datasheet provides a detailed pin layout and description, including power supply pins, test pins, clock inputs, digital inputs, and differential outputs.

Theory of Operation
The DAC uses MSB segmentation for optimal linearity and employs a track-and-hold amplifier to mitigate glitches and improve spectral flatness. The output voltage is determined by the relationship VFS = 0.3xVREF, with an internal reference circuit providing approximately 20dB supply rejection.

Signal Description
Separate power supplies are recommended for digital and analog sections to ensure isolation. The analog outputs require 50 Ω termination to GNDA for full-scale amplitude. The VREF pin allows for external reference voltage to override the internal reference for precise full-scale control.

Specifications:
The RDA012RZ is a digital-to-analog converter (DAC) with clock inputs that can be driven by typical ECL circuits or a differential sinusoidal clock. The clock inputs, CLKP and CLKN, are internally terminated with 50Ω and require a well-decoupled -2.0 volt supply at the VTT pin. The DAC's output phase noise is influenced by the input clock noise and jitter, necessitating a low-jitter clock source. The internal clock driver adds minimal jitter (~100fs). For a 900MHz DAC output, clock jitter should be less than 280fs for a 10-bit equivalent, 62dB SNR.

Data Input and Clocking:
Data inputs adhere to LVDS standards with 100Ω terminations included on the chip. The data input clock is provided by a DSP or ASIC, and the RDA012RZ uses a four-clock deep FIFO for interfacing. Data is written to the FIFO on both edges of the DCLK and read into the DAC register on each rising edge of the DAC clock (CLKI). The FIFO allows for a skew margin of 1.5 clock cycles. A RESET pin is available to enable the read clock of the FIFO.

Performance:
Figures 7 to 11 illustrate the typical performance of the DAC across various Nyquist zones and frequencies. The output and SFDR (Spurious-Free Dynamic Range) are plotted against frequency, demonstrating the DAC's capabilities at different clock and output frequencies.

Package Information:
The RDA012RZ is packaged in a 60-pin QFP with a CuW base for heat dissipation, which should be soldered to copper on a PCB. The package body is electrically tied to GND internally. Dimensions are provided in inches (mm) with a tolerance of ±0.005 inches.

Catalog excerpts

Digital to Analog Converters (DAC) RDA012RZ-1

RDA012RZ 12 Bit 1.0 GS/s Return to Zero DAC Features ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ 12 Bit Resolution 1 GS/s Minimum Sampling Rate 1.5 GS/s Typical 10 Bit Static Linearity LVDS Compliant Digital Inputs Power Supply: -5.2V, +3.3V Input Code Format: Offset Binary Output Swing: 600 mV @ 50 Ω Termination Reference I/O Pin for Accurate Full-Scale Adjustment Return-to-Zero Output for 2nd Nyquist Operation Differential ECL or Sinusoidal Clock Input Fast settling time: < 1ns 0.1% (+/- 2LSB), switching from code 1536 to 2560 (quarter scale) Figure 1. Functional Block Diagram Product Description The RDA012RZ is a 12-bit GaAs DAC with a data update rate over 1Gsample/s. It has been optimized for ultra-high speed applications. The DAC utilizes a segmented current source to reduce the glitch energy and to achieve high linearity performance. For a flat response at the second Nyquist analog band, a track-andattenuate circuit is integrated. Ordering information PART NUMBER RDA012RZ-QP RDA012RZ-DI EVRDA012RZ-QP DESCRIPTION 12 BIT 1GS/s RZDAC, QFP Package 12 BIT 1GS/s RZDAC, DIE RDA012RZ-QP Evaluation Board The product represented in this datasheet is subject to U.S. Export Law as contained in the International Traffic in Arms Regulations (ITAR) Public Domain Information – Previously Approved for Public Release (DOD Office of Security Review, Case 08-S-0606) Teledyne Scientific Company reserves the right to make changes to its product specifications at any time without notice. The information furnished herein is believed to be accurate; however, no responsibility is assumed for its use.

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Digital to Analog Converters (DAC) RDA012RZ-2

Absolute Maximum Ratings Supply Voltages VEEA, VEED to GNDA …………………….. -0.3V to +0.3V VCC to GNDA …………………………..….… 0 V to +3.8 V Temperature Case Temperature…………………………… -40 to +85 °C Junction Temperature….………………………..….. +125 °C Lead, Soldering (10 Seconds) …………………….. +220 °C Storage….……………………………………… -60 to 125 °C The product represented in this datasheet is subject to U.S. Export Law as contained in the International Traffic in Arms Regulations (ITAR) Public Domain Information – Previously Approved for Public Release (DOD Office of Security Review, Case 08-S-0606) Teledyne Scientific Company reserves...

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Digital to Analog Converters (DAC) RDA012RZ-3

DC Electrical Specification Test Conditions (see notes for specific conditions): Room Temperature; VCC = 3.3V; VEEA = -5.2V; VEED = -5.2V; VREF = -2V; VTT = -2V; TMS = RZ Mode; Clock: 1GHz, 0.6Vpp Differential; Outputs Terminated Into 50 Ω to VCC. PARAMETER 1.0 1.1 1.2 2.0 2.1 3.0 3.1 4.0 4.1 4.2 5.0 5.1 5.2 6.0 6.1 6.2 6.3 6.4 7.0 7.1 8.0 8.1 8.2 8.3 8.4 CONDITIONS, NOTE DC TRANSFER FUNCTION Differential Nonlinearity DNL -0.1 Integral Nonlinearity INL -0.1 TEMPERATURE DRIFT Warm-up Time After Power-up CLOCK INPUT (CLKIP, CLKIN) Input Resistance RCLKI Resistance (CLKI P/N) to VTT 45 50 DATA CLOCK...

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Digital to Analog Converters (DAC) RDA012RZ-4

CONDITIONS, NOTE CLOCK INPUTS (CLKIP, CLKIN) Amplitude VCPP,HCLKI Differential Common Mode Voltage VCCM,HCLKI Maximum Frequency FMAX,HCLKI Minimum Frequency FMIN,HCLKI DATA CLOCK INPUTS (DCLKIP, DCLKIN) Amplitude VDPP Differential Common Mode Voltage VDCM DIGITAL INPUTS (DI<0:11>P, DI<0:11>N) Amplitude VDPP Differential Common Mode Voltage VDCM Data In to DCLKI Setup tDTDKST Both Edges of DCLKI Data In to DCLKI Hold tDTDKHD Both Edges of DCLKI TERMINATION VOLTAGE (VTT) Reference Voltage VTT Termination Voltage for CLKI REFERENCE (VREF) Reference Voltage VREF External Reference POWER SUPPLY REQUIREMENTS...

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Digital to Analog Converters (DAC) RDA012RZ-5

Pin Description Pin Layout (TOP view) NAME VCC VEEA VEED FUNCTION VCC Power Supply Analog VEE Power Supply Digital VEE Power Supply Test Pin: Bypass to Ground Test Pin: Bypass to Ground -2V External Reference Voltage Clock Termination Voltage Track Mode Select: Float – RZ Function Ground – ZOH Function RESETP RESETN CLKIP CLKIN DIP 1 DIN 1 1 1 1 DCLKIP DCLKIN OUTP OUTN RESETP / RESETN Is Reset Input CLKIP / CLKIN Is Clock Input DIP / DIN Is Digital Bit I Input. MSB is Bit 11. DCLKIP / DCLKIN Is Data Clock Input OUTP / OUTN Is Differential Output Figure 2. RDA012RZ-QP pinout (top view). The product...

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Digital to Analog Converters (DAC) RDA012RZ-6

The product represented in this datasheet is subject to U.S. Export Law as contained in the International Traffic in Arms Regulations (ITAR) Public Domain Information – Previously Approved for Public Release (DOD Office of Security Review, Case 08-S-0606) Teledyne Scientific Company reserves the right to make changes to its product specifications at any time without notice. The information furnished herein is believed to be accurate; however, no responsibility is assumed for its use.

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Digital to Analog Converters (DAC) RDA012RZ-7

Theory of Operation The DAC employs MSB segmentation, and the number of bits segmented is carefully chosen for the best compromise between static and dynamic linearity. The 12-bit digital data inputs are latched by a master-slave flip-flop immediately after the input buffer to reduce data skew. MSB data bits are decoded into a thermometer code by a two-stage decoding block, and the LSB data bits are transported through the delay equalizer block. The digital data are synchronized again by a second master-slave flip-flop to reduce the switching glitch. The decoded MSB and LSB data bits drive identical...

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Digital to Analog Converters (DAC) RDA012RZ-8

Signal Description POWER SUPPLIES The RDA012RZ has several power supplies. Their names and uses are defined in the pin description section. Different power supply pins are separated inside the chip, and using separate regulators for each supply is recommended for a good isolation between the digital and analog sections of the chip. No power sequencing is required for reliable operation. Also due to the high-breakdown voltage of the device technology, input may be activated upon an unpowered DAC without damaging the part. which are internally terminated with 50Ω. The VTT pin is the termination...

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