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Digital to Analog Converters (DAC) RDA012M4MS

Digital to Analog Converters (DAC)  RDA012M4MS
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Digital to Analog Converters (DAC) RDA012M4MS

Product catalog summary
Overview:
The RDA012M4MS is a high-performance 12-bit digital-to-analog converter (DAC) featuring a 4:1 input multiplexer and a maximum update rate of 1.3 GS/s. It is ideal for high-speed data conversion and synchronization applications, such as I-Q modulation schemes.
Key Features:
  • 12-bit resolution with a 1.3 GS/s sampling rate.
  • 4:1 input multiplexer for efficient data handling.
  • Master-slave operation for synchronized multi-device setups.
  • Differential analog output with a 600 mV swing on 50 Ω termination.
  • Compatible with 3.3V NMOS data inputs and differential ECL or sinusoidal clock inputs.
  • LVDS compatible clock output.
  • 10-bit static linearity and reference output/input pin for full-scale adjustment.
  • Operates on 3.3V and -5.2V power supplies.
Product Description:
The DAC uses a segmented current source to minimize glitch energy and enhance linearity, with internal 50Ω termination for optimal dynamic performance. It outputs a nominal full-scale current of 12mA and interfaces with CMOS ICs through low voltage NMOS compatible digital data inputs.
Ordering Information:
  • RDA012M4MS-DI: 12 BIT 4:1 MUX 1.3GS/s DAC, DIE
  • RDA012M4MS-HD: 12 BIT 4:1 MUX 1.3GS/s DAC, 77 Lead HSD Package
  • RDA012M4MS-QP: 12 BIT 4:1 MUX 1.3GS/s DAC, 88 Lead QFP Package
  • Evaluation boards available for both HD and QP packages.
Specifications:
Absolute Maximum Ratings:
  • Supply voltages: -0.3V to +3.8V
  • RF input voltages: -3V to 1V
  • Temperature range: -40 to +85 °C (case), -60 to 125 °C (storage)
DC Electrical Specifications:
  • Differential nonlinearity (DNL) and integral nonlinearity (INL) both at 4 LSB max.
  • Full-scale output swing: 1140 to 1260 mVpp (differential), 570 to 630 mVpp (single-ended).
  • Power dissipation: Total 3.3W, with specific dissipation for positive and negative supplies.
AC Electrical Specifications:
  • Spurious-Free Dynamic Range (SFDR) varies with frequency, e.g., 56 dBc at 800MHz clock.
  • Data timing setup and hold times specified for optimal performance.
Operating Conditions:
  • High clock input amplitude: 400 to 800 mV (differential ECL).
  • Digital input high and low voltages: 0.9V to VCC and -0.4V to 0.4V, respectively.
  • Operating temperature: -40 to 85 °C (case), with a junction temperature up to 125 °C.
Pin Descriptions:
Detailed pin descriptions and layouts are provided for both HSD and QFP packages, including power supply, reference voltage, clock inputs, and digital bit inputs.
Theory of Operation:
The DAC employs 6-bit segmentation for enhanced performance, with digital data inputs latched by a master-slave flip-flop to reduce data skew. It supports master and slave mode operations for synchronized multi-device configurations, ideal for applications like quadrature modulation.
Procedures:
In slave mode, the MUXDAC synchronizes with a 250MHz LVDS clock from the master MUXDAC. The output clock signals are LVDS compliant and require a 100Ω termination resistor. Data input setup and hold times are specified with respect to the LCLKO.
Analog Output:
The DAC outputs should be connected through a 50 Ω resistor to ground, providing a full-scale amplitude of 0.6 volts, or 1.2 volts differentially. The output termination voltage should not exceed 3 volts for reliable operation.
Reference:
VREFA controls the full-scale amplitude output, with an internal reference circuit providing -2.0 volts. For precise full-scale output, an external voltage reference with low output impedance can be used. The output full-scale voltage is calculated as VFS = 0.3xVREF.
Typical Operating Circuits:
Figures illustrate typical operating circuits using internal and external voltage references, and recommended placement in master-slave mode to minimize LCLK routing.
Performance:
Figures display the output spectrum at various clock frequencies, demonstrating the device's performance.
Package Information:
The RDA012M4MS is available in 77 Lead HSD and 88 Lead QFP packages, both featuring a heatsink slug on the bottom. The thermal resistance from junction to case is approximately 3.5 C/W for the QFP package. Figures provide dimensions and footprints for these packages.
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