Preliminary Specifications in this document are tentative and subject to change S3A7 MCU (High Efficiency MCU) 32-bit ARM® Cortex®-M4 microcontroller High efficiency 48-MHz ARM® Cortex®-M4 microcontroller, up to 1-MB code flash memory, 192-KB SRAM, Segment LCD Controller, Capacitive Touch Sensing Unit, USB 2.0 Full-Speed, 14-Bit A/D Converter, 12-Bit D/A Converter, security and safety features. Features ■ ARM Cortex-M4 Core with Floating Point Unit (FPU)       ARMv7E-M architecture with DSP instruction set Maximum operating frequency: 48 MHz Support for 4-GB address space ARM Memory Protection Unit (MPU) with 8 regions Debug and Trace: ITM, DWT, FPB, TPIU, ETB CoreSight™ debug port: JTAG-DP and SW-DP Up to 1-MB code flash memory 16-KB data flash memory (up to 100,000 erase/write cycles) Up to 192-KB SRAM Flash Cache (FCACHE) Memory Protection Units Memory Mirror Function 128-bit unique ID  USB 2.0 Full-Speed Module (USBFS) - On-chip transceiver with voltage regulator - Compliant with USB Battery Charging Specification 1.2  Serial Communications Interface (SCI) × 6 - UART - Simple IIC - Simple SPI  Serial Peripheral Interface (SPI) × 2  I2C bus interface (IIC) × 3  CAN module (CAN)  Serial Sound Interface (SSI) × 2  SD/MMC Host Interface (SDHI)  Quad Serial Peripheral Interface (QSPI)  IrDA interface  External memory bus - 8- and 16-bit address width 14-Bit A/D Converter (ADC14) 12-Bit D/A Converter (DAC12) × 2 High-Speed Analog Comparator (ACMPHS) × 2 Low-Power Analog Comparator (ACMPLP) × 2 Operational Amplifier (OPAMP) × 4 Temperature Sensor (TSN)  General PWM Timer 32-Bit (GPT32) × 10  Asynchronous General-Purpose Timer (AGT) × 2 - VBATT support  Watchdog Timer (WDT) ECC in SRAM SRAM parity error check Flash area protection ADC self-diagnosis function Clock Frequency Accuracy Measurement Circuit (CAC) Cyclic Redundancy Check (CRC) calculator Data Operation Circuit (DOC) Port Output Enable for GPT (POEG) Independent Watchdog Timer (IWDT) GPIO readback level detection Register write protection Main oscillator stop detection Illegal memory access ■ System and Power Management         Low-power modes Realtime Clock (RTC) with calendar and VBATT support Event Link Controller (ELC) DMA Controller (DMAC) × 4 Data Transfer Controller (DTC) Key Interrupt Function (KINT) Power-on reset Low voltage detection with voltage settings  AES128/256  GHASH  True Random Number Generator (TRNG) ■ Human Machine Interface (HMI)  Segment LCD Controller (SLCDC) - Up to 52 segments × 4 commons - Up to 48 segments × 8 commons  Capacitive Touch Sensing Unit (CTSU) ■ Multiple Clock Sources  Main clock oscillator (MOSC) (1 to 20 MHz when VCC = 2.4 to 5.5 V) (1 to 8 MHz when VCC = 1.8 to 2.4 V) (1 to 4 MHz when VCC = 1.6 to 1.8 V)  Sub-clock oscillator (SOSC) (32.768 kHz)  High-speed on-chip oscillator (HOCO) (24, 32, 48, 64 MHz when VCC = 2.4 to 5.5 V) (24, 32, 48 MHz when VCC = 1.8 to 5.5 V) (24, 32 MHz when VCC = 1.6 to 5.5 V)  Middle-speed on-chip oscillator (MOCO) (8 MHz)  Low-speed on-chip oscillator (LOCO) (32.768 kHz)  Independent watchdog timer OCO (15 kHz)  Clock trim function for HOCO/MOCO/LOCO  Clock out support ■ General Purpose I/O Ports  Up to 124 input/output pins - Up to 3 CMOS input - Up to 121 CMOS input/output - Up to 10 5-V tolerant input/output (when VCC = 3.6 V) - Up to 2 pins high current (20 mA) ■ Operating Temperature and Packages  Ta = –40°C to +85°C - 145-pin LGA(7 mm × 7 mm, 0.5 mm pitch) - 121-pin BGA (8 mm × 8 mm, 0.65 mm pitch) - 100-pin LGA (7 mm × 7 mm, 0.65 mm pitch)  Ta = –40°C to +105

Under development Preliminary document Specifications in this document are tentative and subject to change The S3A7 MCU comprises multiple series of software- and pin-compatible ARM-based 32-bit MCUs that share a common set of Renesas peripherals to facilitate design scalability and efficient platform-based product development. This MCU provides an optimal combination of low-power, high-performance ARM® Cortex®-M4 core running up to 48 MHz with the following features:  Up to 1-MB code flash memory  192-KB SRAM  Segment LCD Controller (SLCDC)  Capacitive Touch Sensing Unit (CTSU)  USB 2.0...

Under development Preliminary document Specifications in this document are tentative and subject to change Functional description Operating mode Two operating modes: - Single-chip mode - SCI/USB boot mode. See section 3, Operating Modes in User's Manual. This MCU has 14 types of resets:  RES# pin reset  Power-on reset  VBATT selected voltage power on reset  Independent watchdog timer reset  Watchdog timer reset  Voltage monitor 0 reset  Voltage monitor 1 reset  Voltage monitor 2 reset  SRAM parity error reset  SRAM ECC error reset  Bus master MPU error reset  Bus slave MPU error reset...

Under development Preliminary document Specifications in this document are tentative and subject to change Functional description The Watchdog Timer (WDT) is a 14-bit down-counter. It can be used to reset this MCU when the counter underflows because the system has run out of control and is unable to refresh the WDT. In addition, a non-maskable interrupt or interrupt can be generated by an underflow. The refresh-permitted period can be set to refresh the counter and used as the condition to detect when the system runs out of control. See section 26, Watchdog Timer (WDT) in User's Manual. Independent...

Under development Preliminary document Specifications in this document are tentative and subject to change Functional description The General PWM Timer (GPT) is a 32-bit timer with 10 channels. PWM waveforms can be generated by controlling the up-counter, down-counter, or the up- and down-counter. In addition, PWM waveforms for controlling brushless DC motors can be generated. The GPT can also be used as a general-purpose timer. See section 23, General PWM Timer (GPT) in User's Manual. Asynchronous General Purpose Timer (AGT) The Asynchronous General Purpose Timer (AGT) is a 16-bit timer that...