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Dual channel digital pulse compression daughter board

Dual channel digital pulse compression daughter board
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Dual channel digital pulse compression daughter board - 1

rai on CI E03 A full spcification can be provided on request. To make an enquiry please email: info@rakon.fr Product Description CI E03 is a digital dual pulse compression module, well suited for RADARS performance enhancement. Analog inputs and outputs make it an ideal replacement for SAW based pulse compression subsystems. Each of the two available channels may be configured as chirp expander or chirp compressor. All the pulse compression parameters are programmable (center frequency, bandwidth, time dispersion, modulation law, weighting function, etc.). CI E03 is provided with FPGA firmware configured according to customer requirements. Features Digital pulse compression module 镕 2 concurrent channels : expander or compressor for each channel 2 x IF analog inputs, 2 x IF analog outputs Օ High precision clock, self sufficient or externally locked BITE function Օ Low profile High BxT compression gain 10 ' 10 Bandwidth B (MHz) Fig. 1 : Maximum B x T compression parameters Applications Օ SAW based pulse compression RADARS upgrade March 28, 2011 CI E03 Revision A2 1 / 10 www.rakon.com

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Dual channel digital pulse compression daughter board - 2

rai on CI E03 Technical description CI E03 functional bloc diagram is featured on Fig. 2. RFOUTB (J5) RFOUTA (J4) REFCLK (J6) RFINA (J2) RFINB (J3) Fig. 2 : CI E03 functional bloc diagram This module is specifically designed to upgrade existing SAW based pulse compression subsystems. Plugged on a specific carrier board, this module may upgrade many existing expanders and/or compressors. With a low size and low profile, it may be embedded in small form factors. This module is able to process on-the-fly 2 independent and concurrent channels. Each channel may be an expander or a compressor....

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Dual channel digital pulse compression daughter board - 3

CI E03 EXP_SELECT Waveforms DAC RFOUT TRIG i imiMg CLOCK Fig. 3 : Expander channel bloc diagram Compressor, featured in Fig. 4, uses a FIR filter whose coefficients are matched to the expander waveform samples. Input data are preliminary translated into baseband, and then are translated again into IF signal. Digital IF signal is then presented to the DAC to be translated into an analog IF signal. For better compatibility with old SAW based subsystems, an adjustable additional delay may be inserted. RF IN ADC To To * baseband FIR F0 DAC RFOUT OSC Timing Fig. 4 : Compressor channel bloc...

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Dual channel digital pulse compression daughter board - 4

DocHdl1OnEBFPR01tmpTarget table.main {} tr.row {} td.cell {} div.block {} div.paragraph {} .font0 { font:8.00pt "Franklin Gothic Medium", sans-serif; } .font1 { font:14.00pt "Franklin Gothic Medium", sans-serif; } .font2 { font:16.00pt "Franklin Gothic Medium", sans-serif; } .font3 { font:38.00pt "Trebuchet MS", sans-serif; } rakon CI E03 Spcifications 1.0 Environmental conditions Line Parameter Test Condition Min. Typ. Max. Unit Operating temperature range_|__|__|__|__|_ 1.1 Forced air cooling (250 ft/min at sea level) VITA 47 Class AC2, FC2 -40 +55 °C 1.2 Conduction cooling with specific...

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Dual channel digital pulse compression daughter board - 5

DocHdl1OnEBFPR01tmpTarget table.main {} tr.row {} td.cell {} div.block {} div.paragraph {} .font0 { font:7.00pt "Franklin Gothic Medium", sans-serif; } .font1 { font:8.00pt "Franklin Gothic Medium", sans-serif; } .font2 { font:14.00pt "Franklin Gothic Medium", sans-serif; } .font3 { font:16.00pt "Franklin Gothic Medium", sans-serif; } CI E03 2.14 Resolution 16 bits 2.15 Bandwidth 100 MHz 2.16 Output level 5 dBm CLK_IN 2.17 Coupling AC 2.18 Impdance 50 O. 2.19 Frequency 10 202 125 MHz Status signais (BOARD_OK, INITTIME_ALM, POWER_OK, TEMP_OK) 2.20 Logic high output voltage IOH = 8 mA 2.9 3.3...

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Dual channel digital pulse compression daughter board - 6

CI E03 3.0 Expander operation Performances Line Parameter Test Condition Min. Typ. Max. Unit 3.1 Stored waveforms | | | | 16 | 3.2 Center frequency (F0) 3 100 -B/2 MHz 3.3 Bandwidth (B) 100 MHz Time dispersion (T) 3.4 16 Exp Wve for each channel 2 expander channels operation 25 us 3.5 1 Exp Wve for each channel _ 2 expander channels operation 400 us 3.6 Minimal Expander delay (TE) 4 Measured from the trigger input rising edge to the center of the output chirp T/2 + 0.3 us 3.7 Additional Expander delay (TE) Measured from the trigger input rising edge to the center of the output chirp 1 s 3.8...

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Dual channel digital pulse compression daughter board - 7

rakon CI E03 4.0 Compressor opration Performances Line Parameter Test Condition Min. Typ. Max. Unit 4.1 Center frequency (F0) 5 100 -B/2 MHz 4.2 Bandwidth (B) 46.9 MHz Time dispersion (T) _|__| 4.3 B < 3 MHz 2 compressor operation 6 267 us 4.4 B < 7 MHz 2 compressor operation 6 48 us 4.5 B < 20 MHz 2 compressor operation 6 5 us 4.6 B < 7 MHz 1 compressor operation 6 178 us 4.7 B < 20 MHz 1 compressor operation 6 21 us 4.8 Compressed pulse width @ -3 dB (x.3dB) 18 ns 4.9 Side lobe level (SLL) 7 35 to 45 dB 4.10 Minimal Compressor delay (TC) 8' 9 Measured from the center of the input chirp,...

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Dual channel digital pulse compression daughter board - 8

CI E03 Mechanical features 5.0 Mechanical features Line Parameter Test Condition Value Unit 5.1 Module size 75 x 120 mm2 5.2 Module height Measured from the upper side of the carrier board 10 mm 5.3 Stacking height 6.4 mm Fig. 6 : CI E03 interfaces drawing March 28, 2011 CI E03 Revision A2 8 / 10 www.rakon.com

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Dual channel digital pulse compression daughter board - 9

CI E03 Interfaces description J1 : Low profile 1.27 pitch, 2x50 pins connector J2 to J6 : MMCX jack connectors 6.0 Interfaces description Line Pin number Name Description 6.1 P1-76 BOARDOK Board status correct output 6.2 P1-56 CFGCCLK FPGA configuration Clock output 6.3 P1-60 CFGCEO FPGA configuration PROM counter input 6.4 P1-50 CFGDIN FPGA configuration Data input 6.5 P1-48 CFGDONE FPGA configuration termination signal output 66 P1-78 CLKEXTEN Enable external reference clock input 6.7 P1-70 INITTIMEALM FPGA configuration time exceeded output 6.8 P1-96 JTAGTCK JTAG Clock input 6.9 P1-90...

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