Digital pulse compression module To make an enquiry please email: [email protected] CI E03 is a digital dual pulse compression module, well suited for RADARS performance enhancement. Analog inputs and outputs make it an ideal replacement for SAW based pulse compression subsystems. Each of the two available channels may be configured as chirp expander or chirp compressor. All the pulse compression parameters are programmable (center frequency, bandwidth, time dispersion, modulation law, weighting function, etc.). CI E03 is provided with FPGA firmware, which will be configured by Rakon, based on customer requirements. • Digital pulse compression module • 2 concurrent channels : Expander or compressor for each channel • 2 x IF analog inputs, 2 x IF analog outputs • High precision clock, self sufficient or externally locked • BITE function • Low profile • High BxT compression gain • SAW based pulse compression RADARS upgrade

Digital pulse compression module CI E03 Technical description CI E03 functional bloc diagram is featured on Fig. 2. DA C 250 MS PS 16 bits CPLD Superv ision BIT E IF Power Control VCFG N_ BOA RD_PD VINMA IN VINVCO Fig. 2 : CI E03 functional bloc diagram This module is specifically designed to upgrade existing SAW based pulse compression subsystems. Plugged on a specific carrier board, this module may upgrade many existing expanders and/or compressors. With a low size and low profile, it may be embedded in small form factors. This module is able to process on-the-fly 2 independent and concurrent...

Digital pulse compression module TRIG Timing Fig. 3 : Expander channel bloc diagram Compressor, featured in Fig. 4, uses a FIR filter whose coefficients are matched to the expander waveform samples. Input data are preliminary translated into baseband, and then are translated again into IF signal. Digital IF signal is then presented to the DAC to be translated into an analog IF signal. For better compatibility with old SAW based subsystems, an adjustable additional delay may be inserted. RF IN Fig. 4 : Compressor channel bloc diagram Fig. 5 represents the maximum time dispersion vs. bandwidth...

Digital pulse compression module

Digital pulse compression module

Digital pulse compression module Logic low output voltage 1 Power dissipation highly depends on channels specifications. Typical figures are given as a rough guide. 2 Frequency should be divisible by 10 MHz

Digital pulse compression module 3.0 Expander operation Performances 3 Some frequency values are not allowed. Center frequency should be related to the master clock by a fractional number. 4 Minimal delay depends slightly on the design. The typical figure is given as a rough guide.

Digital pulse compression module 4.0 Compressor operation Performances 5 Some frequency values are not allowed. Center frequency should be related to the master clock by a fractional number. 6 Assuming 250 MHz FPGA processing, 3.5 points inside the compressed pulse width @ -3dB. 7 Side lobe level depends on B, T and other programmable parameters. Higher values are achievable. 8 Minimal delay depends slightly on the design. The typical figure is given as a rough guide. 9 Assuming B < 7 MHz.

Digital pulse compression module Mechanical features

Digital pulse compression module Interfaces description J1 : Low profile 1.27 pitch, 2x50 pins connector J2 to J6 : MMCX jack connectors

Digital pulse compression module