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InnoSwitch4-CZ

Product catalog summary

Product Overview
The InnoSwitch4-CZ family is an integrated switcher IC designed for high-efficiency flyback power converters. It features a 750 V PowiGaN primary switch, active clamp drive, and synchronous rectification. The IC supports zero voltage switching (ZVS) in both continuous and discontinuous conduction modes (CCM and DCM), enhancing efficiency and reducing transformer size.

Key Features

High integration with a compact footprint.
Steady-state switching frequency up to 140 kHz.
Up to 95% efficiency with less than 30 mW no-load consumption.
Advanced protection features including overvoltage, overcurrent, and over-temperature protection.
Reinforced isolation >4000 VAC and compliance with UL1577 and TUV (EN60950) safety standards.

Applications

High-density flyback designs up to 110 W.
High-efficiency CV/CC power supplies and USB PD adapters.

Technical Specifications

Primary and secondary controllers integrated into a single IC.
FluxLink technology for safe and reliable feedback transmission.
Variable frequency and current limit control for efficient operation.
Primary bypass pin with internal regulator and overvoltage protection.
Auto-restart and latching fault response options.

Protection and Safety

Open SR FET-gate detection and fast input line UV/OV protection.
Multiple output UV fault thresholds and primary over-temperature protection.
Excellent noise immunity meeting EN61000-4 suite standards.

Output Power Table
The document includes a table detailing output power capabilities for different models (INN4073C, INN4074C, INN4075C) across various input conditions, highlighting the adaptability of the IC for different power requirements.

Functional Description
The InnoSwitch4-CZ combines high-voltage power switching with primary and secondary controllers. It uses a novel inductive coupling feedback scheme (FluxLink) for accurate voltage and current information transmission. The primary controller supports ZVS flyback operation, while the secondary controller manages constant voltage and current control, synchronous rectification, and integrated protection features.

Pin Configuration and Description
The document provides detailed descriptions of each pin's function, including connections for current sensing, feedback, synchronous rectification, and voltage output.

Conclusion
The InnoSwitch4-CZ family offers a robust solution for high-efficiency power conversion in compact designs, with comprehensive protection features and regulatory compliance, making it suitable for a wide range of applications in consumer electronics and industrial systems.

HSD to ZVS Delay Programming
To achieve ZVS, a delay is programmed between the turn-off of the ClampZero switch and the conduction of the InnoSwitch4-CZ. This delay is adjusted using a resistor between the HSD and SOURCE pins, with four possible delay settings based on resistance values. The delay is crucial for optimizing ZVS operation.

Primary-Secondary Handshake
The primary controller initially operates without feedback, similar to standard controllers. If no feedback is received, it enters auto-restart mode. The secondary controller takes over control once powered up. A handshake protocol ensures smooth transition and control between primary and secondary controllers, especially after events like line brown-outs.

Audible Noise Reduction
The InnoSwitch4-CZ includes a noise reduction feature that avoids resonant frequencies between 7 kHz and 12 kHz by inhibiting the gate drive to the power switch during this window.

Secondary Controller
Powered by a 4.5 V regulator, the secondary controller manages the synchronous rectifier (SR) FET and regulates output voltage and current. It includes features like minimum off-time, maximum switching frequency, and frequency soft-start to ensure efficient operation.

Output Voltage Protection
The system includes mechanisms to manage output voltage overshoot and feedback pin short detection. It can initiate auto-restart or latch-off sequences to protect against overvoltage conditions.

Applications Example
A schematic for a 20 V, 3.25 A notebook adapter power supply is provided, demonstrating the use of the INN4073C and CPZ1061M components. The design is compliant with DOE Level 6 and EC CoC v5 standards, featuring components for EMI attenuation and protection.

Specifications
The InnoSwitch4-CZ rectifies AC line voltage to provide full-wave rectified DC. Key components include a filter capacitor, Y capacitor for EMI reduction, and resistors for discharging capacitors when disconnected from AC mains. The IC features a self-starting mechanism and uses an auxiliary winding for normal operation.

Operation
The primary side of the IC is connected to a transformer and includes protection against undervoltage and overvoltage. The secondary side provides output voltage and current sensing, driving a MOSFET for synchronous rectification. The IC operates in both continuous and discontinuous conduction modes, adjusting switching cycles based on load.

Protection Mechanisms
The IC includes primary-side overvoltage protection using a Zener diode and secondary-side overvoltage protection with an auto-restart circuit. It also features line undervoltage and overvoltage protection, with recommendations for component selection to ensure effective operation.

Component Selection
Recommendations are provided for selecting capacitors, resistors, and diodes to ensure optimal performance and compliance with voltage and current requirements. The document emphasizes the importance of using suitable components to minimize energy loss and EMI.

Key Considerations
The document outlines conditions for achieving maximum output power, including input voltage requirements, efficiency assumptions, and thermal constraints. It also discusses reducing no-load power consumption and the importance of proper bias winding design.

Primary Sensed OVP (Overvoltage Protection)
The primary-side controller uses the bias winding voltage to detect output voltage amplitude. A Zener diode connected to the PRIMARY BYPASS pin detects secondary overvoltage faults, causing the controller to latch-off or auto-restart. It is recommended to measure the highest voltage at the bias winding output under normal and transient conditions. A Zener diode rated at 1.25 times this voltage ensures OVP protection operates only in fault conditions.

Primary-Side Clamp
The Clamp Zero IC provides soft switching at turn-on of the primary switch. The clamp capacitor stores leakage energy and delivers it to the secondary, preventing voltage spikes. The recommended clamp capacitor value is based on the resonant period of CCLAMP and LLKG, with capacitance ranging from 10 nF to 100 nF. Capacitors should be rated at least 200 V, 1206 or larger size, with X7R dielectric.

Secondary-Side Circuit
A 2.2 mF, 10 V / X7R or X5R capacitor is recommended for the SECONDARY BYPASS pin. The capacitor should be located adjacent to the IC pins. For output voltages below 5 V, an additional active preload is recommended to maintain the SECONDARY BYPASS pin voltage at 4.5 V.

FORWARD Pin Resistor
A 47 W, 5% resistor ensures sufficient IC supply current. Deviating from this value can affect device operation. Acceptable and unacceptable FORWARD pin voltage waveforms are illustrated in figures.

SR FET Operation and Selection
Using an SR FET improves efficiency. The SR FET gate should connect directly to the SYNCHRONOUS RECTIFIER DRIVE pin. A Schottky diode across the SR FET may increase efficiency by 0.2% or more for outputs over 2 A. The voltage rating of the Schottky diode and SR FET should be at least 1.4 times the expected peak inverse voltage.

Output Capacitor
Low ESR aluminum electrolytic or aluminum-polymer capacitors are suitable. Typically, 200 mF to 300 mF of capacitance per ampere of output current is adequate. Capacitors should have a voltage rating higher than the highest output voltage plus margin.

Output Voltage Feedback Circuit
A voltage divider network should ensure the FEEDBACK pin voltage is 1.265 V at the desired output voltage. A 300 pF decoupling capacitor should be placed close to the IC.

Output Overload Protection
The IC limits output current below the VPK threshold and provides constant power above it. The current limit is set by a resistor between the ISENSE and SECONDARY GROUND pins.

Interfacing with USB PD and Rapid Charge Controllers
A microcontroller can alter the feedback voltage divider to adjust output voltage. The interface IC can use the ISENSE pin signal for current and power limiting.

Recommendations for Circuit Board Layout
Single-point grounding, proper placement of bypass capacitors, and minimizing primary loop area are recommended. Thermal considerations include maximizing copper area for heat dissipation. The Y capacitor should be placed to route surge currents away from the IC.

PCB Layout Recommendations

Ensure ESD protection by keeping the output SF FET and filter capacitor loop short.
Place decoupling capacitors for the FEEDBACK and IS-GND pins close to the InnoSwitch4 IC.
Maximize the drain area of the SR FET for effective heat sinking.
Position BPP and BPS capacitors near the InnoSwitch4 IC.
Clamp components should be close to the bulk capacitor, transformer, and InnoSwitch4 drain.
Maximize source copper area for heat sinking.
Connect the Y capacitor to the plus bulk rail on the primary side for surge protection.

EMI Reduction Recommendations

Minimize loop areas in primary and secondary power circuits to reduce EMI.
Use a small capacitor parallel to the clamp diode on the primary side to reduce radiated EMI.
Common mode chokes or shield windings on the transformer can attenuate common mode noise.
Adjust SR switch RC snubber component values to reduce high-frequency EMI.
Use a pi-filter in the input rectifier circuit to reduce low-frequency differential EMI.

Transformer Design Recommendations

Ensure the power supply delivers rated power at the lowest input voltage.
Set switching frequency between 50 kHz to 140 kHz, considering primary inductance and peak current tolerances.
Set reflected output voltage (VOR) to maintain KP = 0.7 at minimum input voltage for universal input.
For high output currents, reduce VOR for highest efficiency.

Design Optimization Considerations

Higher VOR allows increased power delivery at VMIN and reduces voltage stress on output diodes and SR switches.
Higher VOR increases leakage inductance, reducing power supply efficiency.
KP should be close to 0.7 at minimum expected DC bus voltage for most designs.

Core and Safety Margin

Use cores with low loss to reduce thermal challenges.
For safety isolation, a total margin of 6.2 mm is typically required for universal input designs.

Primary Layers and Flux Density

Primary layers should be in the range of 1 ≤ L ≤ 3.
A maximum flux density of 3800 gauss is recommended to prevent core saturation.

Quick Design Checklist

Verify maximum drain voltage and current under worst-case conditions.
Conduct thermal checks to ensure temperature limits are not exceeded.

Design Considerations for PowiGaN Devices

Ensure peak drain voltage is lower than 650 V for all normal operating conditions.
Set VOR to maintain KP = 0.7 at minimum input voltage for universal input.

Absolute Maximum Ratings

DRAIN Pin Voltage: -0.3 V to 750 V
Operating Junction Temperature: -40 to 150 °C
Ambient Temperature: -40 to 105 °C

Specifications
Soldering is specified for copper clad areas of 0.36 sq. inch and 1 sq. inch with 2 oz. copper. The case temperature is measured on the package top. The primary-side current rating is 0.6 A, and the power rating is 1.35 W at 25°C. The secondary-side power rating is 0.125 W at 25°C.

Package Characteristics
Clearance is typically 12.1 mm, creepage is 11.7 mm, and the minimum distance through insulation is 0.4 mm. The transient isolation voltage is at least 6 kV, and the comparative tracking index is 600.

Control Functions
Startup switching frequency ranges from 23 to 27 kHz. Jitter modulation frequency is between 0.80 and 1.70 kHz. Maximum on-time is between 10.5 and 21.5 ms. BPP supply current varies with conditions, and BPP pin voltage is around 5 V with a hysteresis of 0.5 V.

Line Fault Protection
Voltage pin line over-voltage deglitch filter is 3 ms, and the voltage pin rating is 650 V.

Circuit Protection
Standard current limit varies with the BPP capacitor and di/dt conditions. Overload detection frequency ranges from 130 to 151 kHz. Auto-restart on-time is between 75 and 89 ms.

Output Characteristics
ON-state resistance varies with temperature and model. OFF-state drain leakage current is specified for different conditions. Thermal shutdown occurs between 135 and 150°C.

Secondary Feedback
Feedback pin voltage is around 1.265 V. Maximum switching frequency is between 164 and 194 kHz.

Synchronous Rectifier
SR pin drive voltage ranges from 4.3 to 4.7 V. Rise and fall times are specified for a load of 2 nF.

Package Marking and Ordering Information
Includes details on product family, series number, package identifier, and feature codes. MSL rating and ESD/latch-up test conditions are provided.

Notes
Various notes on dimensioning, tolerancing, and recommended practices for ensuring correct current limits are included.

Figures and Graphs
Figures illustrate output characteristics, drain capacitance, power, and synchronous rectifier drive pin voltage limits.

Catalog excerpts

InnoSwitch4-CZ Family Off-Line CV/CC ZVS Flyback Integrated Switcher IC with 750 V PowiGaN, Active Clamp Drive and Synchronous Rectification Product Highlights • Zero voltage switching (ZVS) flyback controller with driver for ClampZeroTM (active clamp IC) • Unique control algorithm to enable ZVS in both DCM and CCM • Robust 750 V PowiGaNTM primary switch • Steady-state switching frequency up to 140 kHz minimizes transformer size • Synchronous rectification driver and secondary-side sensing • Integrated FluxLinkTM, HIPOT-isolated, feedback link • Exceptional CV/CC accuracy, independent of external components • Adjustable accurate output current sense using external sense resistor Highly Integrated, Compact Footprint Primary Switch and Controller S HSD Figure 1. Typical Application schematic EcoSmart™ – Energy Efficient • Up to 95% efficient • Less than 30 mW no-load consumption including line sense Advanced Protection / Safety Features • Open SR FET-gate detection • Fast input line UV/OV protection Optional Features • • • • Variable output voltage, constant current profiles Auto-restart or latching fault response for output OVP/UVP Multiple output UV fault thresholds Latching or hysteretic primary over-temperature protection Figure 2. High Creepage, Safety-Compliant InSOP-24D Package. Full Safety and Regulatory Compliance • • • • Reinforced isolation >4000 VAC 100% production HIPOT testing UL1577 and TUV (EN60950) safety approved Excellent noise immunity enables designs that achieve class “A” performance criteria for EN61000-4 suite; EN61000-4-2, 4-3 (30 V/m), 4-4, 4-5, 4-6, 4-8 (100 A/m) and 4-9 (1000 A/m) Output Power Table 85-264 VAC Product 3 Green Package • Halogen free and RoHS compliant • High density flyback designs up to 110 W • High efficiency CV/CC power supplies • High efficiency USB PD adapters Description The InnoSwitch™4-CZ family of ICs partners with the ClampZero family of active clamp ICs to dramatically improve the efficiency of flyback power converters, particularly those requiring a compact form-factor. The InnoSwitch4-CZ family incorporates primary and secondary controllers and safety-rated feedback into a single IC. Table 1. Output Power Table. Notes: 1. Minimum continuous power in a typical non-ventilated enclosed typical size adapter measured at 40 °C ambient. Max output power is dependent on the design. With condition that package temperature must be < 125 °C. 2. Minimum peak power capability. 3. Package: InSOP-24D. The combination of InnoSwitch4-CZ with ClampZero greatly reduces system and primary switch losses, allowing for extremely high power densities. InnoSwitch4-CZ also incorporates multiple protection features including output overvoltage and over-current limiting, and over-temperature shutdown. Devices are available that support the common combinations of latching and auto-restart protection mode required by applications such as chargers, adapters, consumer electronics and industrial systems. This Product

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LINE INTERFACE CONTROL LOGIC RECEIVER CONTROLLER From Secondary Contoller THERMAL SHUTDOWN Power Switch Figure 3. Primary Controller Block Diagram. FW FW_VALLEY HANDSHAKE /LATCH-OFF SECONDARY LATCH FEEDBACK DRIVER TSMAX OSCILLATOR /TIMER Figure 4. Secondary Controller Block Diagram.

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InnoSwitch4-CZ Pin Functional Description ISENSE (IS) Pin (Pin 1) Connection to the power supply return output terminals. An external current sense resistor should be connected between this and the GND pin. If current regulation is not required, this pin should be tied to the GND pin. SECONDARY GROUND (GND) (Pin 2) GND for the secondary IC. Note this is not the power supply output GND due to the presence of the sense resistor between this and the ISENSE pin. FEEDBACK (FB) Pin (Pin 3) Connection to an external resistor divider to set the power supply output voltage. SECONDARY BYPASS (BPS) Pin...

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InnoSwitch4-CZ is a variable frequency controller allowing CCM/DCM operation for enhanced efficiency and extended output power capability. PRIMARY BYPASS Pin Regulator The PRIMARY BYPASS pin has an internal regulator that charges the PRIMARY BYPASS pin capacitor to VBPP by drawing current from the DRAIN pin whenever the power switch is off. The PRIMARY BYPASS pin is the internal supply voltage node. When the power switch is on, the device operates from the energy stored in the PRIMARY BYPASS pin capacitor. In addition, a shunt regulator clamps the PRIMARY BYPASS pin voltage to VSHUNT when current...

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InnoSwitch4-CZ The auto-restart is reset as soon as an AC reset occurs. SOA Protection In the event that there are two consecutive cycles where the ILIM is reached within ~500 ns (the blanking time + current limit delay time), the controller will skip 2.5 cycles or ~25 ms. This provides sufficient time for the transformer to reset with large capacitive loads without extending the start-up time. Input Line Voltage Monitoring The UNDER/OVER INPUT VOLTAGE pin is used for input undervoltage and overvoltage sensing and protection. A sense resistor is tied between the high-voltage DC bulk capacitor...

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InnoSwitch4-CZ Audible Noise Reduction Engine The InnoSwitch4-CZ features an active audible noise reduction mode whereby the controller (via a “frequency skipping” mode of operation) avoids the resonant band (where the mechanical structure of the power supply is most likely to resonate − increasing noise amplitude) between 7 kHz and 12 kHz – 143 ms and 83 ms. If a secondary controller switch request occurs within this time window from the last conduction cycle, the gate drive to the power switch is inhibited. Secondary Controller As shown in the block diagram in Figure 4, the IC is powered by...

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SR Disable Protection In each cycle SR is only engaged if a set cycle was requested by the secondary controller and the negative edge is detected on the FORWARD pin. In the event that the voltage on the ISENSE pin exceeds approximately 3 times the CC threshold, the SR FET drive is disabled until the surge current has diminished to nominal levels. SR Static Pull-Down To ensure that the SR gate is held low when the secondary is not in control, the SYNCHRONOUS RECTIFIER DRIVE pin has internal pull down circuit “ON” device to pull the pin low and reduce any voltage on the SR gate due to capacitive...

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InnoSwitch4-CZ

InnoSwitch4-CZ

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