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60 GHz Receiver (Rx) Waveguide Module

60 GHz Receiver (Rx) Waveguide Module
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60 GHz Receiver (Rx) Waveguide Module - 1

60 GHz Receiver (Rx) Waveguide Module TECHNICAL DATA SHEET The PEM002 is a highly integrated millimeter wave receiver that covers the 60 GHz global unlicensed spectrum allocations packaged in a standard waveguide module. Receiver architecture is a double conversion, sliding IF with wide bandwidth capability through the conversion chain down to baseband. The I/Q analog interface along with built-in AM and FM detectors provides for flexibility in design and applications. The receiver incorporates a complete waveguide interface with low-loss transition between the chip and the WR15 waveguide port. The integrated package is small and lightweight, with a simple to use multi-pin ST4 connector for power, reference clock, digital control port and baseband signals. Either of two reference clocks can be used for setting 540 MHz or 500 MHz channel spacing. Complete millimeter wave receiver WR-15, UG-385/U flange Operates in the 57 to 66 GHz unlicensed band 6 dB noise figure Up to 1.8 GHz modulation bandwidth I/Q analog baseband interface Integrated AM/ASK and FM/FSK detectors On chip synthesizer covers 57 to 64.8 GHz 500 MHz or 540 MHz step size 285.714 MHz clock for 500 MHz step size 308.572 MHz clock for 540 MHz step size Power, control, signals on ST4 connector Temperature sensor 802.11ad: 58.32, 60.48, 62.64, 64.80 GHz 802.11aj: 59.94, 61.02, 62.10, 63.18 GHz Any Channel (500 MHz or 540 MHz) 57-64.8 GHz Multi-Gbps Digital Communications HD Video Transmission Millimeter Wave Radar Millimeter Wave Radiometry Millimeter Wave Imaging Microwave Temperature Profiling (MTP) Development for 802.11ad and 802.11aj ATE Equipment for 60 GHz Manufacturing Test Click the following link (or enter part number in “SEARCH” on website) to obtain additional part information including price, inventory and certifications: 60 GHz Rec

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60 GHz Receiver (Rx) Waveguide Module - 2

The information contained in this document is accurate to the best of our knowledge and representative of the part described herein. It may be necessary to make modifications to the part and/or the documentation of the part, in order to implement improvements. Pasternack reserves the right to make such changes as required. Unless otherwise stated, all Pasternack Enterprises, Inc. • P.O. Box 16759, Irvine, CA 92623 Sales@Pasternack.com * Techsupport@Pastemack.com ©2013 Pasternack Enterprises All Rights Reserved

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60 GHz Receiver (Rx) Waveguide Module - 3

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60 GHz Receiver (Rx) Waveguide Module - 4

60 GHz Receiver (Rx) Waveguide Module TECHNICAL DATA SHEET PEM002 Table 1 Performance Specifications* Frequency Range Channel Spacing Channel Spacing Modulation Bandwidth Gain, Max Gain, Range Gain, Step Size Image Rejection Sideband Suppression Noise Figure *Test Conditions: Reference Frequency Temperature Input Signal Level IF Bandwidth Output Impedance Output Signal Level 308.571 MHz 25°C -65 dBm Max 50 ohms, 4 output ports: I +/- and Q +/- (100 ohm differential) Referenced to single 50 ohm output for gain specifications Click the following link (or enter part number in “SEARCH” on...

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60 GHz Receiver (Rx) Waveguide Module - 5

60 GHz Receiver (Rx) Waveguide Module TECHNICAL DATA SHEET PEM002 Table 2 Recommended Operating Conditions Description Power Supplies Serial Control Port Logic High Serial Control Port Logic Low Serial Control Port Speed Operating Temperature Reference clock power level specified at 100 ohms differential 2 Baseband voltage at each of the 4 baseband outputs (I +/-, Q +/-) 3 Temperature sensor is a 2N3904 NPN transistor die connected as a diode junction Click the following link (or enter part number in “SEARCH” on website) to obtain additional part information including price, inventory and...

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60 GHz Receiver (Rx) Waveguide Module - 6

60 GHz Receiver (Rx) Waveguide Module TECHNICAL DATA SHEET PEM002 Table 3 Absolute Maximum Ratings Description Power Supplies DATA CLOCK SCANOUT DATA Reference Clock Serial Control Port Logic Low Serial Control Port Logic High Power Dissipation Storage Temperature Assertion of RESET, active high, asynchronously resets all registers Click the following link (or enter part number in “SEARCH” on website) to obtain additional part information including price, inventory and certifications: 60 GHz Receiver (Rx) Waveguide Module PEM002

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60 GHz Receiver (Rx) Waveguide Module - 7

60 GHz Receiver (Rx) Waveguide Module TECHNICAL DATA SHEET Receiver Architecture The PEM002 receiver uses a double conversion superheterodyne architecture with a sliding IF. The IF frequency is at 1/7 the RF carrier frequency, and the VCO is at 2/7 the RF carrier frequency. The LO is 3x the VCO frequency. The LO and IF are generated from a built-in synthesizer that has a step size at the RF carrier frequency of either 500 MHz or 540 MHz depending upon which reference clock frequency is used. The 540 MHz step size uses a 308.571 MHz reference, and the 500 MHz step uses a 285.714 MHz...

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60 GHz Receiver (Rx) Waveguide Module - 8

60 GHz Receiver (Rx) Waveguide Module TECHNICAL DATA SHEET Synthesizer Design The PEM002 receiver uses a double conversion superheterodyne architecture with a sliding IF. The IF frequency is at 1/7 the RF carrier frequency, and the VCO is at 2/7 the RF carrier frequency. The LO is 3x the VCO frequency. The tables below show the RF carrier, IF, VCO and LO for the frequency range from 57 GHz to 64.80 GHz at 540 MHz and 500 MHz channel spacing respectively. The reference clock for the synthesizer at 540 MHz spacing is 308.571 MHz; for 500 MHz spacing it is 285.714 MHz. The loop bandwidth of...

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60 GHz Receiver (Rx) Waveguide Module - 9

60 GHz Receiver (Rx) Waveguide Module TECHNICAL DATA SHEET Digital Control Registers and Serial Interface Protocol - Write Operation The PEM002 is configured via the serial control port which transfers data synchronously to or from (write or read operation) a register location. Register locations are organized into 16, byte-wide (8-bit) locations. The register locations are written to or read from one byte at a time as shown in Figures 5 and 6 respectively. Figure 5 shows the sequence of the digital control signals for the ENABLE, CLOCK and DATA input pins (ST4 connector, pins 39, 36 and 38...

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