UDA1342TS Audio CODEC
45Pages

INTEGRATED CIRCUITS DATA SHEET UDA1342TS Audio CODEC Product specification Supersedes data of 2000 Mar 29 2000 Jul 31

NXP Semiconductors Product specification Audio CODEC UDA1342TS CONTENTS 1 3 PINNING 8 FUNCTIONAL DESCRIPTION 8.1 8.2 8.2.1 8.2.2 8.3 8.4 8.5 8.6 8.7 8.8 8.9 8.10 8.11 8.12 8.13 8.14 8.14.1 8.14.2 8.14.3 8.15 8.15.1 8.15.2 8.15.3 8.15.4 8.15.5 8.16 8.16.1 8.16.2 8.16.3 8.16.4 8.16.5 System clock ADC analog front-end Application with 2 V (RMS) input Double differential mode Decimation filter (ADC) Digital mixer (ADC) Interpolation filter (DAC) Mute Digital mixer (DAC) Noise shaper Filter stream DAC Digital interface Sampling speed Power-on reset Control modes Static pin mode System clock...

NXP Semiconductors Product specification Audio CODEC 1 UDA1342TS FEATURES General • 2.7 to 3.6 V power supply • 5 V tolerant digital inputs • High pin compatibility with UDA1341TS • 24 bits data path • Selectable control via L3-bus interface, I2C-bus interface or static pin control; choice of 2 device addresses in L3-bus and I2C-bus mode Advanced audio configuration • Separate power control for ADC and DAC • 4 channel (2 × stereo) single-ended inputs with programmable gain amplifiers and 2 channel (1 × stereo) single-ended outputs configuration • ADC and Programmable Gain Amplifiers (PGA)...

NXP Semiconductors Product specification Audio CODEC 4 UDA1342TS QUICK REFERENCE DATA SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Supplies VDDA(ADC) ADC analog supply voltage 2.7 3.0 3.6 V VDDA(DAC) DAC analog supply voltage 2.7 3.0 3.6 V VDDD digital supply voltage 2.7 3.0 3.6 V IDDA(ADC) ADC analog supply current 1 ADC + 1 PGA enabled − 10.0 − mA 2 ADCs + 2 PGAs enabled − 20.0 − mA all ADCs + all PGAs power-down − 200 − μA operating − 6.0 − mA DAC power-down − 250 − μA operating − 9.0 − mA ADC power-down − 4.5 − mA DAC power-down − 5.5 − mA −40 − +85 °C − 0.9 − V at −1 dB − −90 − dB...

NXP Semiconductors Product specification Audio CODEC SYMBOL UDA1342TS PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Digital-to-analog convertor Vo(rms) output voltage (RMS value) at 0 dB (FS) digital input; note 1 − 0.9 − V (THD+N)/S48 total harmonic distortion-plus-noise to signal ratio at fs = 48 kHz at 0 dB − −90 − dB at −60 dB; A-weighted − −40 − dB total harmonic distortion-plus-noise to signal ratio at fs = 96 kHz at 0 dB − −83 − dB at −60 dB; A-weighted − −39 − dB S/N48 signal-to-noise ratio at fs = 48 kHz code = 0; A-weighted − 100 − dB S/N96 signal-to-noise ratio at fs = 96 kHz code =...

NXP Semiconductors Product specification Audio CODEC 6 UDA1342TS BLOCK DIAGRAM VDDA(ADC) handbook, full pagewidth VSSA(ADC) 3 VINL2 VDDD 1 10 VADCN 7 11 5 6 8 ADC ADC 2 4 PGA PGA ADC UDA1342TS 9 ADC DECIMATION FILTER DIGITAL MIXER (ADC) 22 23 DC-CANCELLATION FILTER DATAO BCK WS DATAI 18 13 16 L3-BUS/ I2C-BUS INTERFACE DIGITAL INTERFACE 17 VINR2 PGA PGA VINL1 VADCP VSSD 19 14 15 21 DIGITAL MIXER (DAC) DSP FEATURES 12 VINR1 IPSEL STATUS QMUTE L3MODE L3CLOCK L3DATA STATIC SYSCLK INTERPOLATION FILTER 20 NOISE SHAPER DAC VOUTL DAC 26 24 25 VDDA(DAC) 28 Vref Fig.1 Block diagram. 2000 Jul 31 TEST1...

NXP Semiconductors Product specification Audio CODEC 7 UDA1342TS PINNING SYMBOL PIN TYPE DESCRIPTION VSSA(ADC) 1 analog ground pad ADC analog ground VINL1 2 analog input pad ADC input left 1 VDDA(ADC) 3 analog supply pad ADC analog supply voltage VINR1 4 analog input pad ADC input right 1 VADCN 5 analog pad ADC reference voltage N VINL2 6 analog input pad ADC input left 2 VADCP 7 analog pad ADC reference voltage P VINR2 8 analog input pad ADC input right 2 IPSEL 9 5 V tolerant digital input pad channel select input: input left 1 and right 1 or input left 2 and right 2 VDDD 10 digital supply...

NXP Semiconductors Product specification Audio CODEC UDA1342TS 8.2 handbook, halfpage The analog front-end of the UDA1342TS consists of two stereo ADCs with a programmable gain stage (gain from 0 to 24 dB with 3 dB steps) which can be controlled via the L3-bus/I2C-bus interface. 28 Vref VSSA(ADC) 1 27 VSSA(DAC) VINL1 2 VDDA(ADC) 3 ADC analog front-end 26 VOUTL 8.2.1 25 VDDA(DAC) VINR1 4 VADCN 5 In applications in which a 2 V (RMS) input signal is used, a 15 kΩ resistor must be used in series with the input of the ADC (see Fig.3). This forms a voltage divider together with the internal ADC...

NXP Semiconductors Product specification Audio CODEC 8.2.2 UDA1342TS DOUBLE DIFFERENTIAL MODE 8.6 Mute Since the UDA1342TS is equipped with two stereo ADCs, these two pairs of stereo ADCs can be used to convert a single stereo signal to a signal with a higher performance by using the ADCs in the double differential mode. Muting the DAC will result in a cosine roll-off soft mute, using 32 × 32 = 1024 samples in the normal mode: this results in 24 ms at fs = 44.1 kHz. The cosine roll-off curve is illustrated in Fig.4. This mode and the input signals, being channel 1 or 2 as input to the...

NXP Semiconductors Product specification Audio CODEC UDA1342TS to digital interface output handbook, full pagewidth from decimation filter VOLUME AND MUTE master from digital interface input DE-EMPHASIS VOLUME AND MUTE BASS BOOST AND TREBLE + + VOLUME AND MUTE to interpolation filter MGT019 Fig.5 Digital mixer (DAC). 8.8 Noise shaper 8.10 The 5th-order noise shaper operates at 64fs. It shifts in-band quantization noise to frequencies well above the audio band. This noise shaping technique enables high signal-to-noise ratios to be achieved. The noise shaper output is converted into an analog...

NXP Semiconductors Product specification Audio CODEC 8.11 UDA1342TS Sampling speed Important: in the double speed mode an input signal of 0 dB is allowed, but in the quad speed mode the input signal must be limited to −6 dB to prevent the system from clipping. The UDA1342TS operates with sample frequencies from 16 to 110 kHz. This range holds for the CODEC as a whole. The DAC part can be configured in the L3-bus and I2C-bus mode to accept 2 times and even 4 times the data speed (e.g. fs is 96 or 192 kHz), but in these modes not all of the features can be used. Some examples of the input...