TDA8034HN
32Pages

TDA8034HN Low power smart card interface Rev. 3.5 — 13 March 2020 Product data sheet The TDA8034HN is a cost-effective analog interface for asynchronous and synchronous smart cards operating at 5 V, 3 V or 1.8 V. Using few external components, the TDA8034HN provides all supply, protection and control functions between a smart card and the microcontroller. 2. Features and benefits ■ Integrated circuit smart card interface in an HVQFN24 package ■ 5 V, 3 V or 1.8 V smart card supply ■ Very low power consumption in Deep Shutdown mode ■ Three protected half-duplex bidirectional buffered I/O lines (C4, C7 and C8) ■ VCC regulation: ♦ 5 V, 3 V or 1.8 V + 5 % using two low ESR multilayer ceramic capacitors: one of 220 nF and one of 470 nF ♦ current spikes of 40 nA/s (VCC = 5 V and 3 V) or 15 nA/s (VCC =1.8 V) up to 20 MHz, with controlled rise and fall times and filtered overload detection of approximately 120 mA ■ Thermal and short-circuit protection for all card contacts ■ Automatic activation and deactivation sequences triggered by a short-circuit, card take-off, overheating, falling VDD, VDD(INTF) or VDDP ■ Enhanced card-side ElectroStatic Discharge (ESD) protection of > 8 kV ■ External clock input up to 26 MHz connected to pin XTAL1 ■ Card clock generation up to 20 MHz using pins CLKDIV1 and CLKDIV2 with synchronous frequency changes of fxtal, V2 fxtal, V4 fxtal or Vfc fxtal ■ Non-inverted control of pin RST using pin RSTIN ■ Compatible with ISO 7816, NDS and EMVCo4.3 1 payment systems ■ Supply supervisor for killing spikes during power on and off: ♦ using a fixed threshold ♦ using an external resistor bridge with threshold adjustment ■ Built-in debouncing on card presence contacts (typically 8 ms) ■ Multiplexed status signal using pin OFFN

Low power smart card interface ■ Pay TV ■ Electronic payment ■ Identification ■ Bank card readers 4. Quick reference data Table 1. Quick reference data VDDP = 5V; VDD = 3.3 V; VDD(INTF) =3.3 V; fxtal =10 MHz; GND = 0 V; Tamb = 25 °C; unless otherwise specified. TDA8034HN All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2020. All rights reserved. Product data sheet Rev. 3.5 — 13 March 2020 2 of 32

[1] To meet these specifications, VCC should be decoupled to pin GND using two ceramic multilayer capacitors of low ESR with values of either 100 nF or one 220 nF and one 470 nF. 5. Ordering information Table 2. Ordering information All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2020. All rights reserved. Product data sheet 3 of 32 Rev. 3.5 — 13 March 2020

Low power smart card interface VOLTAGE SENSE INTERNAL OSCILLATOR INTERNAL REFERENCE CLKUP ALARMN RSTIN CMDVCCN OFFN CLKDIV1 CLKDIV2 RESET GENERATOR CLOCK GENERATOR CLOCK CIRCUIT CARD CONNECTOR THERMAL PROTECTION ALARMN, CLKUP, EN1, PVCC, EN4, EN3, EN2 and CLK are internal signals. (1) Optional external resistor bridge, if not required connect pin PORADJ to VDD(INTF) Block diagram Product data sheet All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2020. All rights reserved.

Low power smart card interface terminal 1 index areax VDD(INTF) VCC_SEL2 RSTIN VCC_SEL1 CMDVCCN CLKDIV1 RRRRRR <38 PORADJ Q7 VDD (J6 VDDP Q5 VCC <34 rst (31 CLK All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2020. All rights rese^ed. Product data sheet 5 of 32 Rev. 3.5 — 13 March 2020

Table 3. Pin description ...continued [1] I = input, O = output, I/O = input/output, G = ground and P = power supply. [2] If pin PRESN is LOW, the card is considered to be present. During card insertion, debouncing can occur on these signals. To counter this, the TDA8034HN has a built-in debouncing timer (typically 8 ms). [3] Uses an internal 11 kQ pull-up resistor connected to pin VCC. [4] Uses an internal 20 kQ pull-up resistor connected to pin VDD(INTF). [5] Uses an internal 10kW pull-up resistor connected to pin VDD(INTF) 8. Functional description Remark: Throughout this document the...

Low power smart card interface In case the 3 power supply VDD, VDDP, VDD(INTF) are connected together (VDD =VDDP= VDD(INTF)) and if the power up slope is faster than 1ms (10%-90% slope<1ms), a deep shutdown sequence must be performed once the supplies have reached steady state; this means CMDVCCN is set high while VCC_SEL1 and VCC_SEL2 forced to low level (see Section 8.6 “Deep shutdown mode”). 8.2 Voltage supervisor VDD(INTF) R1 REFERENCE VOLTAGE Voltage supervisor circuit The voltage supervisor monitors the voltage of the VDDP, VDD and VDD(INTF) supplies providing both Power-On Reset...

Low power smart card interface Vth + Vhys Vth VDD ALARMN (internal signal) Fig 4. Voltage supervisor waveforms 8.3 Clock circuits The clock signal from pin CLK to the card is either supplied by an external clock signal connected to pin XTAL1 or generated using a crystal connected between pins XTAL1 and XTAL2. The TDA8034HN automatically detects if an external clock is connected to XTAL1, eliminating the need for a separate pin to select the clock source. Automatic clock source detection is performed on each activation command (falling edge of the signal on pin CMDVCCN). The presence of an...

Low power smart card interface When the frequency of the clock signal on pin CLK is either fxtai, V2 fxtai, V4 fxtai or Vs fxtai. the frequency dividers guarantee a duty cycle between 45 % and 55 %. Table 4. Clock configuration 8.4 Input and output circuits When pins I/O and I/OUC are pulled HIGH using an 11 kQ resistor between pins I/O and VCC and/or between pins I/OUC and VDD(INTF), both lines enter the idle state. Pin I/O is referenced to VCC and pin I/OUC to VDD(INTF), thus allowing operation at VCC ^ VDD(INTF). The first side on which a falling edge occurs becomes the master. An...

Low power smart card interface deactivation sequence shutdown shutdown OFFN PRESN Fig 6. Shutdown and Deep shutdown mode activation/deactivation 8.7 Activation sequence The following device activation sequence is applied when using an external clock; see Figure 7: 2. The internal oscillator is triggered (t0). 3. The internal oscillator changes to high frequency (t1). 4. VCc rises from either 0 V to 3 V or 0 V to 5 V on a controlled slope (t2). 5. Pins I/OUC, AUX1UC and AUX2UC are driven HIGH (t3). 6. The clock on pin CLK is applied to the C3 contact (t4). 7. Pin RST is enabled (t5)....