SC16C2550B 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs Rev. 05 — 12 January 2009 Product data sheet 1. General description The SC16C2550B is a two channel Universal Asynchronous Receiver and Transmitter (UART) used for serial data communications. Its principal function is to convert parallel data into serial data and vice versa. The UART can handle serial data rates up to 5 Mbit/s. The SC16C2550B is pin compatible with the ST16C2550. It will power-up to be functionally equivalent to the 16C2450. The SC16C2550B provides enhanced UART functions with 16-byte FIFOs, modem control interface, DMA mode data transfer. The DMA mode data transfer is controlled by the FIFO trigger levels and the TXRDYn and RXRDYn signals. On-board status registers provide the user with error indications and operational status. System interrupts and modem control features may be tailored by software to meet specic user requirements. An internal loopback capability allows on-board diagnostics. Independent programmable baud rate generators are provided to select transmit and receive baud rates. The SC16C2550B operates at 5 V, 3.3 V and 2.5 V and the industrial temperature range, and is available in plastic PLCC44, LQFP48, DIP40 and HVQFN32 packages. 2. Features I I I I I I I I I I I I I 1. 2 channel UART 5 V, 3.3 V and 2.5 V operation 5 V tolerant on input only pins1 Industrial temperature range Pin and functionally compatible to 16C2450 and software compatible with INS8250, SC16C550 Up to 5 Mbit/s data rate at 5 V and 3.3 V and 3 Mbit/s at 2.5 V 16-byte transmit FIFO to reduce the bandwidth requirement of the external CPU 16-byte receive FIFO with error ags to reduce the bandwidth requirement of the external CPU Independent transmit and receive UART control Four selectable Receive FIFO interrupt trigger levels Software selectable baud rate generator Standard asynchronous error and framing bits (Start, Stop and Parity Overrun Break) Transmit, Receive, Line Status and Data Set interrupts independently controlled For data bus pins D7 to D0, see Table 23 “Limiting values”.

SC16C2550B NXP Semiconductors 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs I Fully programmable character formatting: N 5-bit, 6-bit, 7-bit or 8-bit characters N Even, odd or no-parity formats N 1, 11⁄2 or 2-stop bit N Baud generation (DC to 5 Mbit/s) I False start-bit detection I Complete status reporting capabilities I 3-state output TTL drive capabilities for bidirectional data bus and control bus I Line break generation and detection I Internal diagnostic capabilities: N Loopback controls for communications link fault isolation I Prioritized interrupt system controls...

SC16C2550B NXP Semiconductors 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs 4. Block diagram SC16C2550B A0 to A2 CSA CSB TRANSMIT SHIFT REGISTER TXA, TXB RECEIVE FIFO REGISTER RECEIVE SHIFT REGISTER RXA, RXB DATA BUS AND CONTROL LOGIC REGISTER SELECT LOGIC INTERCONNECT BUS LINES AND CONTROL SIGNALS D0 to D7 IOR IOW RESET TRANSMIT FIFO REGISTER DTRA, DTRB RTSA, RTSB OP2A, OP2B INTA, INTB TXRDYA, TXRDYB RXRDYA, RXRDYB INTERRUPT CONTROL LOGIC CLOCK AND BAUD RATE GENERATOR MODEM CONTROL LOGIC CTSA, CTSB RIA, RIB CDA, CDB DSRA, DSRB 002aaa595 XTAL1 Fig 1. XTAL2 Block diagram...

SC16C2550B NXP Semiconductors 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs 5.2 Pin description Table 3. Pin description Symbol Pin Type Description HVQFN32 DIP40 PLCC44 LQFP48 A0 19 28 31 28 I Address 0 select bit. Internal register address selection. A1 18 27 30 27 I Address 1 select bit. Internal register address selection. A2 17 26 29 26 I Address 2 select bit. Internal register address selection. CSA 8 14 16 10 I CSB 9 15 17 11 I Chip Select A, B (active LOW). This function is associated with individual channels, A through B. These pins enable data transfers between...

SC16C2550B NXP Semiconductors 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs Table 3. Pin description …continued Symbol Pin Type Description HVQFN32 DIP40 PLCC44 LQFP48 RESET 24 35 39 36 I Reset (active HIGH). A logic 1 on this pin will reset the internal registers and all the outputs. The UART transmitter output and the receiver input will be disabled during reset time. (See Section 7.10 “SC16C2550B external reset condition” for initialization details.) RXRDYA - - 34 31 O RXRDYB - - 23 18 O Receive Ready A, B (active LOW). This function is associated with PLCC44 and LQFP48...

SC16C2550B NXP Semiconductors 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs Table 3. Pin description …continued Symbol Pin Type Description Data Set Ready (active LOW). These inputs are associated with individual UART channels, A through B. A logic 0 on this pin indicates the modem or data set is powered-on and is ready for data exchange with the UART. This pin has no effect on the UART’s transmit or receive operation. HVQFN32 DIP40 PLCC44 LQFP48 DSRA - 37 41 39 I DSRB - 22 25 20 I DTRA - 33 37 34 O DTRB - 34 38 35 O RIA - 39 43 41 I RIB - 23 26 21 I RTSA 23 32 36 33 O RTSB...

SC16C2550B NXP Semiconductors 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs 6. Functional description The SC16C2550B provides serial asynchronous receive data synchronization, parallel-to-serial and serial-to-parallel data conversions for both the transmitter and receiver sections. These functions are necessary for converting the serial data stream into parallel data that is required with digital data systems. Synchronization for the serial data stream is accomplished by adding start and stop bits to the transmit data to form a data character (character orientated protocol)....

SC16C2550B NXP Semiconductors 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs Table 4. Serial port selection Chip Select Function CSA, CSB = 1 none CSA = 0 UART channel A CSB = 0 UART channel B 6.2 Internal registers The SC16C2550B provides two sets of internal registers (A and B) consisting of 12 registers each for monitoring and controlling the functions of each channel of the UART. These registers are shown in Table 5. The UART registers function as data holding registers (THR/RHR), interrupt status and control registers (IER/ISR), a FIFO Control Register (FCR), line status...