SAF3560HV Terrestrial digital radio processor
20Pages

SAF3560 Terrestrial digital radio processor Rev. 4 — 29 November 2011 Product short data sheet 1. General description The SAF3560 is a digital radio processor that demodulates and processes digital terrestrial baseband signals, such as HD Radio signals, into audio signals and digital data signals. IF PROCESSING TUNER1 baseband I2S interface blend digital audio SPI2 OPTIONAL AUDIO POST PROCESSING AND STEREO AUDIO DAC blended audio (analog) SERIAL NOR-FLASH MEMORY SAF3560 SDRAM baseband I2S interface I2C-bus or SPI1 RENDERING OF DATA: IF PROCESSING TUNER2 MICROPROCESSOR LIVE TRAFFIC REPORTS WEATHER SPORTS SCORES STOCK TICKER 001aal423 (1) Second input only supported by specific types (see Table 3) Fig 1. System block diagram Major benefits of terrestrial radio processor systems with SAF3560 are: • • • • • • Compatibility with conventional baseband radio reception ICs Dramatically improved reception and sound quality CD-sound quality without noise, interference and multipath fading for FM Providing new data services HD Radio reception including audio processing Voltage partitioning of I/Os

SAF3560 NXP Semiconductors Terrestrial digital radio processor System designers can add digital terrestrial radio capability in a simple and inexpensive way through the SAF3560. The SAF3560 decodes digital radio input to provide digital audio and also processes digital data. Multiple interfaces give flexibility while integrating the SAF3560 into the receiver system. 2. Features and benefits 2.1 HD Radio technology HD Radio signal decoding for AM and FM digital audio Dual HD Radio support for support of 2nd station for background scanning and data service Front-end to baseband interface...

SAF3560 NXP Semiconductors Terrestrial digital radio processor 2.4 Other peripheral interfaces Two I2C-bus interfaces Three Serial Peripheral Interfaces (SPI) One UART interface Five individual GPIO pins for applications and diagnostics One JTAG interface for diagnostics 2.5 Miscellaneous One internal clock oscillator and two internal Phase-Locked Loops (PLL) Can run on external crystal or reference clock from an external IC Powerful signal and audio processing core architecture Qualified in accordance with AEC-Q100 3. Quick reference data Table 1. Power supply characteristics After...

SAF3560 NXP Semiconductors Terrestrial digital radio processor 4. Ordering information Table 2. Ordering information Type number Package Name Description Version SAF3560HV/V1100 HLQFP144 plastic thermal enhanced low profile quad flat package; 144 leads; body 20 20 1.4 mm; exposed die pad SOT612-4 SAF3560HV/V1101 HLQFP144 plastic thermal enhanced low profile quad flat package; 144 leads; body 20 20 1.4 mm; exposed die pad SOT612-4 SAF3560HV/V1102 HLQFP144 plastic thermal enhanced low profile quad flat package; 144 leads; body 20 20 1.4 mm; exposed die pad SOT612-4 SAF3560HV/V1103 HLQFP144...

xxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx x xxxxxxxxxxxxxx xxxxxxxxxx xxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxx xxxxxxxxxxxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxx x x Rev. 4 — 29 November 2011 All information provided in this document is subject to legal disclaimers. FLASH CGU JTAG CLOCK JTAG CONTROLLER NXP Semiconductors RESET SPI1 (host) XTAL 5. Block...

SAF3560 NXP Semiconductors Terrestrial digital radio processor Table 4. Pin allocation table (HLQFP144) …continued Pin Symbol Pin Symbol Pin Symbol Pin Symbol 93 SDRAM_DIO12 94 SDRAM_DIO13 95 SDRAM_DIO14 96 VDDD(SDRAM)(3V3) 97 SDRAM_DIO15 98 SDRAM_WE_N 99 SDRAM_DQM0 100 SDRAM_DQM1 101 VDDD(SDRAM)(3V3) 102 VDDD(MEM)(1V2) 103 SDRAM_BA0 104 SDRAM_BA1 105 SDRAM_CS_N 106 SDRAM_RAS_N 107 VDDD(SDRAM)(3V3) 108 SDRAM_CAS_N 109 SDRAM_CLKE 110 SDRAM_AO0 111 SDRAM_AO1 112 VDDD(SDRAM)(3V3) 113 SDRAM_AO2 114 SDRAM_AO3 115 SDRAM_AO4 116 VDDD(SDRAM)(3V3) 117 SDRAM_AO5 118 SDRAM_AO6 119 SDRAM_AO7 120...

SAF3560 NXP Semiconductors Terrestrial digital radio processor Table 6. Pin description (power supplies) …continued Symbol Pin Type[1] Description VDDD(DSP)(3V3) 64 and 71 P DSP digital supply voltage (3.3 V) VDDD(JTAG)(3V3) 138 P JTAG digital supply voltage (3.3 V) VDDD(MC)(3V3) 6, 15, 21 and 28 P microcontroller digital supply voltage (3.3 V) VDDD(SDRAM)(3V3) 80, 85, 90, 96, 101, 107, P 112, 116, 122 and 129 SDRAM digital supply voltage (3.3 V) VDDD(MEM)(1V2) 70, 102 and 143 memory digital supply voltage (1.2 V) [1] P Table 15 defines the pin type. Table 7. Pin description (baseband...

SAF3560 NXP Semiconductors Terrestrial digital radio processor Table 8. Pin description (generic tuner interface) Symbol Type[1] Pin Description GPIO interface GPIO4 40 IOZU general purpose input and output port 4 GPIO3 39 IOZU general purpose input and output port 3 GPIO2 38 IOZU general purpose input and output port 2 GPIO1 37 IOZU general purpose input and output port 1 GPIO0 36 IOZU general purpose input and output port 0 SPI3_MISO 30 IOZU-H master input, slave output of third SPI interface SPI3_MOSI 31 IOZU-H master output, slave input of third SPI interface SPI3_SCLK 32 SPI3 interface...

SAF3560 NXP Semiconductors Terrestrial digital radio processor Table 9. Pin description (SDRAM interface) …continued Symbol Pin Type[1] Description SDRAM_AO5 117 OZU address output bit 5 SDRAM_AO4 115 OZU address output bit 4 SDRAM_AO3 114 OZU address output bit 3 SDRAM_AO2 113 OZU address output bit 2 SDRAM_AO1 111 OZU address output bit 1 SDRAM_AO0 110 OZU address output bit 0 SDRAM_BA1 104 OZU bit 1 of bank address output SDRAM_BA0 103 OZU bit 0 of bank address output SDRAM_CAS_N 108 OZU column address selector output (active LOW) SDRAM_CLK 127 OZU clock output SDRAM_CLKE 109 OZU clock...

SAF3560 NXP Semiconductors Terrestrial digital radio processor Table 11. Pin description (external host microcontroller interface) Symbol Pin Type[1] Description CLKOUT 1 OL clock output; clock source and clock frequency are programmable through software RESET_N 2 IZU-H master reset input from host microcontroller (active LOW) I2C-bus interface (master and slave) I2C2_DA 9 IOZD-H data acknowledge input and output of the I2C-bus interface 2 I2C2_SCL 7 IOZU serial clock input and output of the I2C-bus interface 2 I2C2_SDA 8 IOZU serial data input and output of the I2C-bus interface 2 I2C1_DA...