SAC57D54H
77Pages

NXP Semiconductors Data Sheet: Technical Data SAC57D54H Features • ARM™ Cortex-A5, 32-bit CPU – Supports ARMv7- ISA – 32 KB Instruction cache, 32 KB Data cache – NEON SIMD Media Processing Engine – FPU supporting double precision floating point operations – Memory Management Unit – GIC Interrupt Controller – Up to 320 MHz • ARM™ Cortex-M4, 32-bit CPU – Supports ARMv7 - ISA – 16 KB Instruction cache, 16 KB Data cache – 64 KB Tightly-Coupled Memory (TCM) – Single Precision FPU – NVIC Interrupts Controller – 1.25 DMIPS per MHz integer performance – Up to 160 MHz • I/O Processor – ARM™ Cortex-M0+, 32-bit CPU – Intelligent Stepper Motor Drive • Debug functionality – Run-time debug control of cores and visibility of system resources using the Debug Access Port (DAP) – IEEE 1149.1/ IEEE 1149.7 System JTAG Controller (SJTAG) – Program and Data Trace support (16-bit data width) implemented by the ARM Trace Port Interface Unit (TPIU) Trace capture • Timer – Four 8-channel Flextimer modules (FTM) – Two 4 channel System Timer Module (STM) – Three Software WatchDog Timers (SWT) – One 8 channel Periodic Interrupt Timer (PIT) – Autonomous Real Time Counter (RTC) • Analog – 1 x 24 channel, 12-bit analog-to-digital converter (ADC) – 2 analog comparators (CMP) • Security – Cryptographic Services Engine (CSE) • Memory subsystem – System Memory Protection Unit – 4 MB on-chip flash supported with the flash controller – 1 MB on-chip SRAM with ECC – 1.3 MB on-chip Graphics SRAM with FlexECC • Safety – ISO26262 ASIL-B compliance – Password and Device Security (PASS) supporting advanced censorship and life-cycle management – One Fault Collection and Control Unit (FCCU) to collect faults and issue interrupts • Supports wake-up from low power modes via the WKPU controller • Multiple operating modes – Includes enhanced low power operation • On-chip voltage regulator – External 3.3 V input supply – Option for direct, external supply of core voltage – Low Voltage Detect (LVD) and High Voltage Detect (HVD) on various supplies and regulators • Memory interfaces – 2 x Dual QuadSPI Serial flash controllers – Supports SDR and DDR serial flash – Support for 3.3 V Hyperflash (Spansion) – DRAM controller supporting SDR and DDR2 • Clock interfaces – 8-40 MHz external crystal (FXOSC) – 16 MHz IRC (FIRC) – 128 kHz IRC (SIRC) – 32 kHz external crystal (SXOSC) – Clock Monitor Unit (CMU) – Frequency modulated phase-locked loop (FMPLL) – Real Time Counter (RTC)

• Graphics interfaces – Vivante GC355 GPU supporting OpenVG 1.1 – 2 x 2D-ACE Display Controllers (with inline Head-Up-Display warping) – Digital RGB, TCON_0 (RSDS), TCON_1 and OpenLDI/LVDS output options – Digital Video Input (VIU4) – RLE Decoder for memory-memory decompression – 40x4 segment LCD driver, reconfigurable as 38x6 or 36x8 • Cluster peripherals – Sound Generator Module (SGM) – 6 Stepper Motor Drivers with Stepper Stall Detect • Communication – Ethernet 10/100 + AVB (ENET) – MLB50 – FlexCAN x 3 – DSPI x 5 – LINFlexD x 3 (1 x Master/Slave, 2 x Master only) – I2C x 2 • eDMA...

6.1.2 Analog Comparator (CMP) electrical specifications 6.2.2 Slow Oscillator (SXOSC) electrical specifications .. 32 6.2.3 Fast internal RC Oscillator (FIRC) electrical 6.2.4 Slow internal RC oscillator (SIRC) electrical 6.3.1.2 Flash memory Array Integrity and 6.3.1.3 Flash memory module life 6.3.1.4 Data retention vs program/erase cycles. 36 6.3.1.5 Flash memory AC timing 6.3.1.6 Flash read wait state and address

6.5.4.1 TCON RSDS electrical specifications... 63

Block diagram Temp Sensor I/O Ctrl Reset Ctrl System Modules System Bus Memory Protection SJTAG TPIU Port Splitter Clock Monitor Interrupt Router Peripheral Interrupts Figure 1. High level block diagram

Family comparison RDC - 8 domain, 1MDAC per master, 2x MDAC per CPU., Port Splitter Priority Manager EE Emulation Secure Flash memory OTP Figure 2. Detailed block diagram 2 Family comparison The table below provides a summary of the different members of the SAC57D5xx Low/ Mid-Line Instrument Cluster family and their features. Note that not all features are available simultaneously on all packages. Table 1. Feature sets Product Features Table continues on the next page...

Family comparison Table 1. Feature sets (continued) Table continues on the next page...

Ordering parts Table 1. Feature sets (continued) 1. GRAM can be reconfigured as ECC RAM 2. DDR2 interface only available in BGA package option 3 Ordering parts 3.1 Determining valid orderable parts Valid orderable part numbers are provided on the web. 1. To determine the orderable part numbers for this device, go to www.nxp.com and perform a part number search for the following device number: SAC57D5xx.

4 General 4.1 Absolute maximum ratings NOTE Functional operating conditions appear in the DC electrical characteristics. Absolute maximum ratings are stress ratings only, and functional operation at the maximum values is not guaranteed. Stress beyond the listed maximum values may affect device reliability or cause permanent damage to the device. Table 2. Absolute maximum ratings

1. All parameters are with reference to Vss unless otherwise specified. 2. A crossover current of up to 2 mA may be experienced if VDD12 is ramped up before VDDE_A supply. This current is only an electrical crossover but has no functional implications, and should be removed when VDDE_A ramps up to its functional operating range. 3. Not available for input voltage, only for decoupling internal regulators. 4. VDDA_REF is only available on the 516 BGA package. 5. DDR_VREF is expected to be equal to 0.5 x VDDE_DDR and to track VDDE_DDR DC variations as measured at the device pins. Ensure VDD_LV...