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MSC8256

Product catalog summary

Overview: The MSC8256 is a six-core digital signal processor (DSP) developed by Freescale Semiconductor. It features six StarCore SC3850 DSP subsystems, each with an SC3850 DSP core, 32 Kbyte L1 instruction and data caches, and a unified 512 Kbyte L2 cache configurable as M2 memory. The processor supports various power modes and includes an extended programmable interrupt controller (EPIC), timers, and debug support.

Key Features:

Six DSP cores operating at 1 GHz or 800 MHz.
1056 Kbyte M3 memory with power-saving options.
High-speed serial interfaces including Serial RapidIO and PCI Express.
Two DDR controllers supporting DDR2 and DDR3 with up to 2 Gbyte total memory.
DMA controller with 32 channels optimized for DDR SDRAM.
QUICC Engine technology for Ethernet interfaces and SPI support.
Low power CMOS design with advanced power management.

Electrical Characteristics:

Maximum ratings and recommended operating conditions are specified for optimal performance.
Thermal characteristics and clock input requirements are detailed for system design considerations.

Hardware Design Considerations:

Guidelines for power supply ramp-up sequence and PLL power supply design.
Clock and timing signal board layout considerations are provided.
Connectivity guidelines for remote power supply sensing.

Package Information: The MSC8256 is available in a 783-ball FC-PBGA package, with detailed pin assignments and signal lists provided for board design.

Figures and Diagrams: The document includes block diagrams of the MSC8256 and its subsystems, as well as various timing and connection diagrams to aid in hardware implementation.

Signal List: The document lists signals by ball number, detailing the signal name, pin type, and associated power rail. Signals are categorized based on their function, such as input (I), output (O), and input/output (I/O), and are associated with specific power rails like GVDD1, GVDD2, SXCVDD1, SXCVDD2, and NVDD.

Power and Ground Connections: Numerous power (e.g., GVDD1, GVDD2, VDD) and ground (VSS) connections are specified, indicating the necessary power supply and grounding for the processor's operation.

Reserved and Non-User Signals: Certain signals are marked as reserved or non-user, indicating they should be left unconnected or are used for manufacturing and testing purposes only. This ensures compatibility with future device revisions.

Signal Functions and Configuration:

Signal functions during power-on reset are determined by the RCW source type.
Functionality selection for TDM, RGMII, RapidIO, SGMII, and PCI Express is based on RCW bit values.
GPIO functions are configured via GPIO register setup, with details in the MSC8256 Reference Manual.
Open-drain signals and internal 20 KΩ pull-up resistors can be configured through GPIO register programming.
Power supply connections require external filters as detailed in the PLL Power Supply Design Considerations section.

Electrical Characteristics:

Detailed information on power considerations, DC/AC electrical characteristics, and AC timing specifications is provided.
Maximum ratings are stress ratings only, and functional operation at these limits is not guaranteed.
Recommended operating conditions ensure proper device operation, with specific voltage and temperature ranges provided.

Maximum Ratings:

Core and PLL supply voltages range from -0.3 to 1.1 V.
DDR memory supply voltages vary for DDR2 and DDR3 modes.
Operating temperature ranges from -40 to 105°C, with storage temperatures from -55 to 150°C.

Recommended Operating Conditions:

Core and memory supply voltages have specified minimum, nominal, and maximum values.
Operating temperature ranges are specified for standard, higher, and extended conditions.
Typical power consumption is detailed for devices running at 1 GHz and 800 MHz under specific conditions.

Thermal Characteristics:

Thermal resistance values are provided for different airflow conditions and board configurations.

CLKIN Requirements:

Specifications for CLKIN signal characteristics, including duty cycle, slew rate, and jitter, are provided.

DDR SDRAM DC Electrical Characteristics:

Separate specifications are provided for DDR2 and DDR3 interfaces, including reference voltages and input/output characteristics.

High-Speed Serial Interface (HSSI) DC Electrical Characteristics:

The MSC8256 includes SerDes ports for high-speed serial interface applications, with specific DC requirements for reference clocks and data lanes.
Differential signal definitions and characteristics are detailed for transmitter and receiver operations.

Specifications:
The document outlines the electrical characteristics and requirements for various interfaces in the MSC8256 Six-Core Digital Signal Processor. Key specifications include:

Differential Output Signal: The peak differential voltage (VDIFFp) is 500 mV, and the peak-to-peak differential voltage (VDIFFp-p) is 1000 mV.
SerDes Reference Clock Receiver: The reference clock inputs are internally AC-coupled with a 50-Ω termination. The common mode voltage (Vcm) is calculated as the arithmetic mean of the two complementary output voltages.
DC-Level Requirements: The document specifies DC-level requirements for SerDes reference clocks, PCI Express, Serial RapidIO, and SGMII configurations. For example, the differential clock input amplitude must be between 400 mV and 1600 mV peak-to-peak.

Procedures:
The document describes the procedures for connecting and configuring the SerDes reference clocks and other interfaces:

Connection Modes: The SerDes reference clock can be connected in differential or single-ended modes, with specific requirements for each.
AC and DC Coupling: Guidelines are provided for both AC-coupled and DC-coupled connections, including current and voltage requirements.

Norms and Standards:
The document references compliance with the PCI Express Base Specification, Revision 1.0a, and provides detailed transmitter and receiver specifications for PCI Express and other interfaces.

Recommendations:
Recommendations include ensuring that the external reference clock driver can handle the termination requirements and that the input amplitude requirements are met through appropriate coupling methods.

Tables and Figures:
The document includes several tables and figures that provide detailed specifications and diagrams for the electrical characteristics of the interfaces. Key data includes:

Table 11: PCI Express Differential Transmitter Output DC Specifications.
Table 12: PCI Express Differential Receiver Input DC Specifications.
Figures: Diagrams illustrating the reference circuits for SerDes data lane transmitter and receiver, and the DC requirements for different connection schemes.

1. Electrical Characteristics: The document outlines the AC and DC electrical characteristics for various interfaces, including DDR SDRAM and PCI Express. Key parameters such as output low voltage (VOL) and high voltage (VOH) are specified for different conditions.

2. AC Timing Characteristics: This section details the AC timing specifications for DDR SDRAM and PCI Express interfaces.

2.1 DDR SDRAM AC Timing Specifications:

Input AC Timing: Tables 18 and 19 provide input AC timing specifications for DDR2 and DDR3 SDRAM interfaces at 1.8 V and 1.5 V, respectively. Key parameters include AC input low (VIL) and high (VIH) voltages.
Output AC Timing: Table 21 outlines the output AC timing specifications, including cycle time (tMCK) and setup/hold times for various signals.
Differential Timing: Tables 22 and 23 provide differential timing specifications for DDR2 and DDR3 SDRAM interfaces, focusing on cross-point voltages.

2.2 HSSI AC Timing Specifications:

SerDes Reference Clock: Table 24 lists AC requirements for SerDes reference clocks, including frequency range and jitter specifications.
PCI Express AC Specifications: Tables 25 and 26 define AC specifications for PCI Express transmitter (Tx) and receiver (Rx) lines, focusing on unit interval (UI) and eye width.

Figures and Diagrams: The document includes several figures illustrating timing diagrams and test loads for DDR SDRAM and PCI Express interfaces, aiding in understanding the timing relationships and measurement points.

Notes and Recommendations: The document provides notes on measurement conditions and assumptions, emphasizing the importance of operating within specified conditions for accurate performance.

1. PCI Express and Serial RapidIO Specifications:

PCI Express (2.5 Gbps) Differential Receiver Input AC Specifications are detailed, focusing on jitter and unit intervals.
Serial RapidIO Transmitter and Receiver AC Timing Specifications are provided, excluding REF_CLK jitter, with parameters like deterministic jitter and total jitter.

2. SGMII AC Timing Specifications:

Transmitter and receiver AC characteristics are measured at specific outputs and inputs, with detailed jitter specifications.

3. TDM Timing:

Includes input and output AC timing specifications for the TDM interface, with detailed timing diagrams and notes on signal timing.

4. Ethernet Timing:

Describes AC electrical characteristics for the Ethernet interface, including management interface timing and RGMII AC timing specifications.

5. SPI Timing:

Lists SPI input and output AC timing specifications, with diagrams for master and slave modes.

6. Asynchronous Signal Timing:

Details the timing specifications for asynchronous signals used in various interfaces like GPIO, EE port, and I2C.

7. JTAG Signals:

Provides JTAG timing specifications with diagrams for test clock input, boundary scan, and test access port timing.

Key Points:

Jitter specifications are critical across various interfaces, ensuring reliable data transmission.
Timing diagrams and tables provide precise measurements for setup, hold times, and signal transitions.
Specifications are valid under recommended operating conditions, emphasizing the importance of adhering to these conditions for optimal performance.

Hardware Design Considerations for MSC8256 Device

1. Power Supply Ramp-Up Sequence

1.1 Clock, Reset, and Supply Coordination: Proper coordination of clock, reset, and power supplies is crucial. PORESET and TRST must be asserted during supply ramp-up. CLKIN should toggle at least 32 cycles before PORESET deassertion.

1.2 Power-On Ramp Time: The power-on ramp rate for all voltage supplies must be controlled to avoid triggering ESD circuitry. The ramp rate should not exceed 36000 V/s.

1.3 Power Supply Guidelines: Specific coupling and sequencing guidelines are provided for various power rails, including M3VDD, PLL_AVDD, and RapidIO supplies. External voltage should not exceed I/O supply voltage by more than 0.6 V.

1.4 Reset Guidelines: Different connection schemes are recommended depending on whether a debugger is used.

2. PLL Power Supply Design Considerations

Each PLL power supply requires an external RC filter. The components for the filter are specified, and the filter should be placed close to the PLLn_AVDD inputs for optimal noise filtering.

3. Clock and Timing Signal Board Layout Considerations

Clock and timing signal paths should be short and routed with 50 Ω impedance. A serial termination resistor is recommended to minimize signal reflection.

4. SGMII AC-Coupled Serial Link Connection Example

An example of a 4-wire AC-coupled serial link connection is provided, with additional layout suggestions available in related documentation.

5. Connectivity Guidelines

5.1 DDR Memory Related Pins: Guidelines for connecting DDR-related pins are provided for scenarios where the DDR interface is not used, used with 32-bit DDR memory, or when ECC is not used.

5.2 HSSI-Related Pins: Connectivity guidelines are provided for scenarios where the RapidIO interface or specific HSSI lanes are not used.

5.3 RGMII Ethernet Related Pins: Recommendations are provided for connecting Ethernet-related pins when alternate functions are not used.

Specifications and Pin Connections:
The document provides detailed pin connection guidelines for the MSC8256 Six-Core Digital Signal Processor. It includes tables specifying connections for RGMII, GE Management, TDM, and miscellaneous pins when certain interfaces are not used. For example, when the RGMII interface is not used, specific pins like GE1_RX_CTL should be connected to GND.

Remote Power Supply Sensing:
Guidelines are provided for selecting connections for remote power supply sensing to ensure consistent input power levels. Specific pins like VDD and VSS are recommended for remote sensing to avoid application and device failure.

Ordering Information:
Details on how to order the MSC8256 processor are provided, including product availability and specifications such as core frequency and temperature range.

Package Information:
The document includes mechanical information about the 783-ball FC-PBGA package, with dimensions and tolerancing details.

Product Documentation:
A list of supporting documents is provided, including technical data sheets, reference manuals, and application notes related to the MSC8256 device.

Revision History:
The document includes a revision history table, detailing updates made in various versions from April 2010 to July 2013.

Catalog excerpts

MO Freescale Semiconductor Data Sheet MSC8256 Six-Core Digital Signal Processor • Six StarCore SC3850 DSP subsystems, each with an SC3850 DSP core, 32 Kbyte L1 instruction cache, 32 Kbyte L1 data cache, unified 512 Kbyte L2 cache configurable as M2 memory in 64 Kbyte increments, memory management unit (MMU), extended programmable interrupt controller (EPIC), two general-purpose 32-bit timers, debug and profiling support, low-power Wait, Stop, and power-down processing modes, and ECC/EDC support. • Chip-level arbitration and switching system (CLASS) that provides full fabric non-blocking arbitration between the cores and other initiators and the M2 memory, shared M3 memory, DDR SRAM controllers, device configuration control and status registers, and other targets. • 1056 Kbyte 128-bit wide M3 memory, 1024 Kbytes of which can be turned off to save power. • 96 Kbyte boot ROM. • Three input clocks (one global and two differential). • Five PLLs (three global and two Serial RapidIO PLLs). • Two DDR controllers with up to a 400 MHz clock (800 MHz data rate), 64/32 bit data bus, supporting up to a total 2 Gbyte in up to four banks (two per controller) and support for DDR2 and DDR3. • DMA controller with 32 unidirectional channels supporting 16 memory-to-memory channels with up to 1024 buffer descriptors per channel, and programmable priority, buffer, and multiplexing configuration. It is optimized for DDR SDRAM. • Up to four independent TDM modules with programmable word size (2, 4, 8, or 16-bit), hardware-base A-law/^-law conversion, up to 62.5 Mbps data rate for each TDM link, and with glueless interface to E1 or T1 framers that can interface with H-MVIP/H.110 devices, TSI, and codecs such as AC-97. • High-speed serial interface that supports two Serial RapidIO interfaces, one PCI Express interface, and two SGMII interfaces (multiplexed). The Serial RapidIO interfaces support 1x/4x operation up to 3.125 Gbaud with a single messaging unit and two DMA units. The PCI Express controller supports 32- and 64-bit addressing, x4, x2, and x1 link. • QUICC Engine technology subsystem with dual RISC processors, 48 Kbyte multi-master RAM, 48 Kbyte instruction RAM, supporting two communication controllers for two Gigabit Ethernet interfaces (RGMII or SGMII), to offload scheduling tasks from the DSP cores, and an SPI. • I/O Interrupt Concentrator consolidates all chip maskable interrupt and non-maskable interrupt sources and routes then to INT_OUT, NMTOuT, and the cores. • UART that permits full-duplex operation with a bit rate of up to 6.25 Mbps. • Two general-purpose 32-bit timers for RTOS support per SC3850 core, four timer modules with four 16-bit fully programmable timers, and eight software watchdog timers (SWT). • Eight programmable hardware semaphores. • Up to 32 virtual interrupts and a virtual NMI asserted by simple write access. • I2C interface. • Up to 32 GPIO ports, sixteen of which can be configured as external interrupts. • Boot interface options include Ethernet, Serial RapidIO interface, I2C, and SPI. • Supports standard JTAG interface • Low power CMOS design, with low-power standby and power-down modes, and optimized power-management circuitry. • 45 nm SOI CMOS technology.

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Pin Assignment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 1.1 FC-PBGA Ball Layout Diagram . . . . . . . . . . . . . . . . . . . .4 1.2 Signal List By Ball Location. . . . . . . . . . . . . . . . . . . . . . .5 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 2.1 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 2.2 Recommended Operating Conditions . . . . . . . . . . . . . .25 2.3 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . .26 2.4 CLKIN Requirements . . . . . . . . . . . . ....

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I/O-Interrupt Concentrator UART Clocks Timers Reset High-Speed Serial Interface 32 Kbyte 32 Kbyte L1 L1 ICache DCache QUICCEngine Subsystem Dual RISC Processors Serial Serial PCI RapidIO RapidIO Expr 512 Kbyte L2 Cache / M2 Memory Six DSP Cores at 1 GHz or 800 MHz Four TDMs 256-Channels each Semaphores Virtual Interrupts Boot ROM I2 C Other Modules 4x 3.125 Gbaud PCI-EX 1x/2x/4x Two SGMII 4x 3.125 Gbaud Two SGMII Note: The arrow direction indicates master or slave. Figure 1. MSC8256 Block Diagram 128 bits master bus to CLASS 128 bits slave bus from CLASS 512 Kbyte L2 Cache / M2 Memory TWB Task...

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The top view of the FC-PBGA package is shown in Figure 3 with the ball location index numbers.

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1.2 Signal List By Ball Location Table 1 presents the signal list sorted by ball number. When designing a board, make sure that the power rail for each signal is appropriately considered. The specified power rail must be tied to the voltage level specified in this document if any of the related signal functions are used (active) Note: The information in Table 1 and Table 2 distinguishes among three concepts. First, the power pins are the balls of the device package used to supply specific power levels for different device subsystems (as opposed to signals). Second, the power rails are the electrical...

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