MSC8256
70Pages

MO Freescale Semiconductor Data Sheet MSC8256 Six-Core Digital Signal Processor • Six StarCore SC3850 DSP subsystems, each with an SC3850 DSP core, 32 Kbyte L1 instruction cache, 32 Kbyte L1 data cache, unified 512 Kbyte L2 cache configurable as M2 memory in 64 Kbyte increments, memory management unit (MMU), extended programmable interrupt controller (EPIC), two general-purpose 32-bit timers, debug and profiling support, low-power Wait, Stop, and power-down processing modes, and ECC/EDC support. • Chip-level arbitration and switching system (CLASS) that provides full fabric non-blocking arbitration between the cores and other initiators and the M2 memory, shared M3 memory, DDR SRAM controllers, device configuration control and status registers, and other targets. • 1056 Kbyte 128-bit wide M3 memory, 1024 Kbytes of which can be turned off to save power. • 96 Kbyte boot ROM. • Three input clocks (one global and two differential). • Five PLLs (three global and two Serial RapidIO PLLs). • Two DDR controllers with up to a 400 MHz clock (800 MHz data rate), 64/32 bit data bus, supporting up to a total 2 Gbyte in up to four banks (two per controller) and support for DDR2 and DDR3. • DMA controller with 32 unidirectional channels supporting 16 memory-to-memory channels with up to 1024 buffer descriptors per channel, and programmable priority, buffer, and multiplexing configuration. It is optimized for DDR SDRAM. • Up to four independent TDM modules with programmable word size (2, 4, 8, or 16-bit), hardware-base A-law/^-law conversion, up to 62.5 Mbps data rate for each TDM link, and with glueless interface to E1 or T1 framers that can interface with H-MVIP/H.110 devices, TSI, and codecs such as AC-97. • High-speed serial interface that supports two Serial RapidIO interfaces, one PCI Express interface, and two SGMII interfaces (multiplexed). The Serial RapidIO interfaces support 1x/4x operation up to 3.125 Gbaud with a single messaging unit and two DMA units. The PCI Express controller supports 32- and 64-bit addressing, x4, x2, and x1 link. • QUICC Engine technology subsystem with dual RISC processors, 48 Kbyte multi-master RAM, 48 Kbyte instruction RAM, supporting two communication controllers for two Gigabit Ethernet interfaces (RGMII or SGMII), to offload scheduling tasks from the DSP cores, and an SPI. • I/O Interrupt Concentrator consolidates all chip maskable interrupt and non-maskable interrupt sources and routes then to INT_OUT, NMTOuT, and the cores. • UART that permits full-duplex operation with a bit rate of up to 6.25 Mbps. • Two general-purpose 32-bit timers for RTOS support per SC3850 core, four timer modules with four 16-bit fully programmable timers, and eight software watchdog timers (SWT). • Eight programmable hardware semaphores. • Up to 32 virtual interrupts and a virtual NMI asserted by simple write access. • I2C interface. • Up to 32 GPIO ports, sixteen of which can be configured as external interrupts. • Boot interface options include Ethernet, Serial RapidIO interface, I2C, and SPI. • Supports standard JTAG interface • Low power CMOS design, with low-power standby and power-down modes, and optimized power-management circuitry. • 45 nm SOI CMOS technology.

Pin Assignment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 1.1 FC-PBGA Ball Layout Diagram . . . . . . . . . . . . . . . . . . . .4 1.2 Signal List By Ball Location. . . . . . . . . . . . . . . . . . . . . . .5 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 2.1 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 2.2 Recommended Operating Conditions . . . . . . . . . . . . . .25 2.3 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . .26 2.4 CLKIN Requirements . . . . . . . . . . . ....

I/O-Interrupt Concentrator UART Clocks Timers Reset High-Speed Serial Interface 32 Kbyte 32 Kbyte L1 L1 ICache DCache QUICCEngine Subsystem Dual RISC Processors Serial Serial PCI RapidIO RapidIO Expr 512 Kbyte L2 Cache / M2 Memory Six DSP Cores at 1 GHz or 800 MHz Four TDMs 256-Channels each Semaphores Virtual Interrupts Boot ROM I2 C Other Modules 4x 3.125 Gbaud PCI-EX 1x/2x/4x Two SGMII 4x 3.125 Gbaud Two SGMII Note: The arrow direction indicates master or slave. Figure 1. MSC8256 Block Diagram 128 bits master bus to CLASS 128 bits slave bus from CLASS 512 Kbyte L2 Cache / M2 Memory TWB...

The top view of the FC-PBGA package is shown in Figure 3 with the ball location index numbers.

1.2 Signal List By Ball Location Table 1 presents the signal list sorted by ball number. When designing a board, make sure that the power rail for each signal is appropriately considered. The specified power rail must be tied to the voltage level specified in this document if any of the related signal functions are used (active) Note: The information in Table 1 and Table 2 distinguishes among three concepts. First, the power pins are the balls of the device package used to supply specific power levels for different device subsystems (as opposed to signals). Second, the power rails are the...

Table 1. Signal List by Ball Number (continued) MSC8256 Six-Core Digital Signal Processor Data Sheet, Rev. 6 6 Freescale Semiconductor

Table 1. Signal List by Ball Number (continued) MSC8256 Six-Core Digital Signal Processor Data Sheet, Rev. 6 Freescale Semiconductor 7

Table 1. Signal List by Ball Number (continued) MSC8256 Six-Core Digital Signal Processor Data Sheet, Rev. 6 8 Freescale Semiconductor

Table 1. Signal List by Ball Number (continued) MSC8256 Six-Core Digital Signal Processor Data Sheet, Rev. 6 Freescale Semiconductor 9

Table 1. Signal List by Ball Number (continued) MSC8256 Six-Core Digital Signal Processor Data Sheet, Rev. 6 10 Freescale Semiconductor

Table 1. Signal List by Ball Number (continued) MSC8256 Six-Core Digital Signal Processor Data Sheet, Rev. 6 Freescale Semiconductor 11