LH75401/LH75411 System-on-Chip
63Pages

Preliminary data sheet sists of two low-cost 16/32-bit System-on-Chip (SoC) • LH75401 — contains the superset of features. COMMON FEATURES • Highly Integrated System-on-Chip • High Performance (84 MHz CPU Speed) - Internal PLL Driven or External Clock Driven - Crystal Oscillator/Internal PLL Can Operate with Input Frequency Range of 14 MHz to 20 MHz - 16 kB Tightly Coupled Memory (TCM) SRAM • Clock and Power Management - Low Power Modes: Standby, Sleep, Stop • Eight Channel, 10-bit Analog-to-Digital Converter • Integrated Touch Screen Controller • Serial interfaces - Two 16C550-type UARTs supporting baud rates up to 921,600 baud (requires crystal frequency of - One 82510-type UART supporting baud rates up to 3,225,600 baud (requires a system clock of • Synchronous Serial Port - Motorola SPI™ - National Semiconductor Microwire™ • Three Counter/Timers - Capture/Compare/PWM Compatibility • Low-Voltage Detector • JTAG Debug Interface and Boundary Scan • Color and Grayscale Liquid Crystal Display (LCD) - 12-bit (4,096) Direct Mode Color, up to VGA - 8-bit (256) Direct or Palettized Color, up to SVGA - 4-bit (16) Direct Mode Color/Grayscale, up to XGA - Supports STN, TFT, HR-TFT, and AD-TFT • CAN Controller that supports CAN version 2.0B. • Color and Grayscale LCD Controller (LCDC) - 12-bit (4,096) Direct Mode Color, up to VGA - 8-bit (256) Direct or Palettized Color, up to SVGA - 4-bit (16) Direct Mode Color/Grayscale, up to XGA - Supports STN, TFT, HR-TFT, and AD-TFT Preliminary data sheet

ORDERING INFORMATION Table 1. Ordering information Preliminary data sheet

ADVANCED HIGH RESET CONTROL REAL TIME SERIAL PORT Figure 1. LH75401 Block Diagram Preliminary data sheet

ADVANCED HIGH RESET CONTROL REAL TIME SERIAL PORT TOUCH PANEL Figure 2. LH75411 Block Diagram Preliminary data sheet

Preliminary data sheet

Table 2. LH75401 Numerical Pin List Preliminary data sheet

Table 2. LH75401 Numerical Pin List (Cont'd) Preliminary data sheet

Table 2. LH75401 Numerical Pin List (Cont'd) Preliminary data sheet

Table 2. LH75401 Numerical Pin List (Cont'd) 1. Signal is selectable as pull-up, pull-down, or no pull-up/pull-down via the I/O Configuration peripheral. 2. CMOS Schmitt trigger input. 3. Signals preceded with 'n' are active LOW. 4. Crystal Oscillator Inputs should be driven to 1.8 V ±10 % (MAX.) 5. LINREGEN activation requires a 0 Q pull-up to VDD. Preliminary data sheet

Table 3. LH75401 Signal Descriptions Preliminary data sheet

Table 3. LH75401 Signal Descriptions (Cont'd) Preliminary data sheet

Table 3. LH75401 Signal Descriptions (Cont'd) Preliminary data sheet

Table 3. LH75401 Signal Descriptions (Cont'd) Preliminary data sheet

Table 3. LH75401 Signal Descriptions (Cont'd) 1. These pin numbers have multiplexed functions. 2. Signals preceded with 'n' are active LOW. Preliminary data sheet

Table 4. LH75411 Numerical Pin List Preliminary data sheet

Table 4. LH75411 Numerical Pin List (Cont'd) Preliminary data sheet

Table 4. LH75411 Numerical Pin List (Cont'd) Preliminary data sheet

Table 4. LH75411 Numerical Pin List (Cont'd) 1. Signal is selectable as pull-up, pull-down, or no pull-up/pull-down via the I/O Configuration peripheral. 2. CMOS Schmitt trigger input. 3. Signals preceded with 'n' are active LOW. 4. Crystal Oscillator Inputs should be driven to 1.8 V ±10 % (MAX.) 5. LINREGEN activation requires a 0 Q pull-up to VDD. Preliminary data sheet

Table 5. LH75411 Signal Descriptions Preliminary data sheet

Table 5. LH75411 Signal Descriptions (Cont'd) Preliminary data sheet

Table 5. LH75411 Signal Descriptions (Cont'd) Preliminary data sheet

Table 5. LH75411 Signal Descriptions (Cont'd) Preliminary data sheet

Table 5. LH75411 Signal Descriptions (Cont'd) 1. These pin numbers have multiplexed functions. 2. Signals preceded with 'n' are active LOW. Preliminary data sheet

Figure 4. LH75401 System Application Example FUNCTIONAL OVERVIEW ARM7TDMI-S core with an Advanced High-Performance embedded RISC processor and a member of the ARM7 Thumb family of processors. For more information, visit ARM Advanced Microcontroller Bus Architecture (AMBA) 2.0 internal bus protocol. Three AHB masters control access to external memory and on-chip peripherals: • The ARM processor fetches instructions and trans- fers data • The Direct Memory Access Controller (DMAC) trans- fers from memory to memory, from peripheral to memory, and from memory to peripheral • The LCDC refreshes...

Reset Generation EXTERNAL RESETS Two external signals generate resets to the • nPOR sets all internal registers to their default state when asserted. It is used as a Power-On Reset. • nRESETIN sets all internal registers, except the JTAG circuitry, to their default state when asserted. When nPOR is asserted, nRESETIN defines the microcontroller Test Mode. When nPOR is released, nRESETIN behaves during Reset as described INTERNAL RESETS There are two types of Internal Resets generated: • System Reset System and RTC Resets are asserted by: • An External Reset (a logic LOW signal on the exter-...

Table 8. APB Peripheral Register Mapping Static Random Access Memory Controller of Static Random Access Memory (SRAM) organized • 16 kB of TCM 0 Wait State SRAM is available to the • 16 kB of internal SRAM is available as an AHB slave and accessible via processor, DMAC, and LCDC. Each memory segment is 512 MB, though the TCM and internal SRAMs are 16 kB each in size. Any access beyond the first 16 kB is mapped to the lower 16 kB, but does not cause a data or prefetch abort. Static Memory Controller (SMC) The Static Memory Controller (SMC) is an AMBA AHB slave peripheral that provides the...

Color LCD Controller (CLCDC) The CLCDC is an AMBA master-slave module that connects to the AHB. It translates pixel-coded data into the required formats and timings to drive single/dual monochrome and color LCD panels. Packets of pixel- coded data are fed, via the AHB interface, to two inde- pendently programmable, 32-bit-wide DMA FIFOs. Each FIFO is 16 words deep by 32 bits wide. The CLCDC generates a single combined interrupt to the Vectored Interrupt Controller (VIC) when an interrupt condition becomes true for upper/lower panel DMA FIFO underflow, base address update significa- tion,...