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i.MX RT1064 Crossover Processors for Industrial Products
i.MX RT1064 Crossover Processors for Industrial Products
The i.MX RT1064 is a processor family by NXP featuring the Arm Cortex-M7 core, operating up to 528 MHz. It includes 4 MB on-chip Flash and 1 MB on-chip RAM, with advanced power management and various memory interfaces. It supports peripherals like WLAN, Bluetooth, GPS, displays, and camera sensors, making it suitable for industrial applications such as HMIs and motor control.
The processor supports a single Arm Cortex-M7 core with 32 KB L1 instruction and data caches, a full-featured FPU, and up to 512 KB I-TCM and D-TCM. It includes a 128 KB Boot ROM, 4 MB on-chip Flash, and 1 MB on-chip RAM. External memory interfaces include SDRAM, NAND FLASH, and SPI NOR FLASH. It also features timers, PWMs, and various connectivity options like USB, Ethernet, UARTs, I2C, and SPI.
The i.MX RT1064 system includes internal memory, multimedia connectivity, external memory interfaces, and system control features. It integrates security functions like High Assurance Boot and Data Co-Processor, and supports analog interfaces such as ADCs and DACs.
The processor contains various digital and analog modules, including Analog Comparators, ADCs, a Bus Encryption Engine, and a Central Security Unit. It also features a Debug Access Port for real-time access and a DCDC Converter for power supply generation.
Part numbers MIMXRT1064CVL5A and MIMXRT1064CVJ5A are available, with features like 528 MHz operation, 4 MB Flash, and various connectivity and security options. They are packaged in 196-pin MAPBGA with different dimensions and pitch sizes.
- Supports nominal run and low power standby modes.
- Run mode output: 0.9 ~ 1.3 V.
- Standby mode output: 0.9 ~ 1.0 V.
- Includes over current and over voltage detection.
- Features a 32-channel DMA engine for complex data transfers with minimal processor intervention.
- DMA_MUX can multiplex up to 128 DMA request sources to the 32 DMA channels.
- Interfaces with position/speed sensors using five input signals: PHASEA, PHASEB, INDEX, TRIGGER, and HOME.
- Decodes shaft position, revolution count, and speed.
- Supports 10/100 Mbit/s Ethernet/IEEE 802.3 networks.
- Requires external transceiver interface and function.
- Dedicated hardware supports IEEE 1588 standard.
- Monitors external circuits and software flow, providing a backup mechanism to the internal WDOG.
- Does not reset the system but provides an independent trigger pin for external circuit safety.
- Full implementation of CAN protocol specification, Version 2.0 B.
- Supports standard and extended message frames.
- Supports a wide range of protocols including UART, I2C, SPI, I2S, camera interface, display interface, and PWM waveform generation.
- Functional in low power mode if the clock remains active.
- Contains four PWM sub-modules for controlling half-bridge power stages.
- Generates various switching patterns and sophisticated waveforms.
- 1 MB of on-chip RAM, flexibly allocated to I-TCM, D-TCM, and OCRAM in 32 KB granularity.
- Interfaces with one or two external serial flash devices with up to four bidirectional data lines.
- Supports up to 32 bits of I/O for general purpose input/output to external ICs.
- 32-bit timer with programmable prescaler and compare and capture register.
- Provides precise interrupts at regular intervals with minimal processor intervention.
- 16-bit peripheral for keypad matrix interface or general purpose I/O.
- Supports 8 x 8 external keypad matrix with multiple-key detection.
- General purpose display controller for a wide range of display devices.
- Supports both synchronous and asynchronous LCD devices.
- Efficient interface to an I2C bus as a master.
- Efficient interface to an SPI bus as a master and/or a slave.
- Operates in stop modes with an appropriate clock.
- Supports 7- or 8-bit data words, 1 or 2 stop bits, and programmable parity.
- Programmable baud rates up to 5 Mbps.
- Generates 2-channel medium quality PWM-like audio via two standard digital GPIO pins.
- High-performance pixel processor for color-space conversion, alpha blending, and rotation.
- Provides four time channels with various controls for individual and multi-channel features.
- Interface between the Arm advanced high-performance bus and the ROM.
- 96 KB ROM used by the Cortex-M7 core during boot up.
- Provides the clock source for the Real-Time Clock module.
- High reliability independent timer ensuring software execution as planned.
- Resets the MCU if not serviced within a certain period.
- Supports full duplex serial interfaces with frame synchronization.
- Generates a 512-bit entropy for entropy consuming modules or post processing functions.
- Multi-standard memory controller supporting multiple external memories with shared address and data pins.
- Provides JTAG interface for production, testing, and system debugging.
- Incorporates three security modes for protecting against unauthorized accesses.
- Includes Secure Real Time Clock, Security State Machine, and Master Key Control.
- Standard audio file transfer format with Transmitter and Receiver functionality.
- Implements a temperature sensor/conversion function based on temperature-dependent voltage to time conversion.
- Supports 4-wire and 5-wire resistive touch panel.
- Contains two high-speed OTG 2.0 modules with integrated HS USB PHYs.
- Fully compliant with MMC, SD, and SDIO command/response sets and Physical Layer specifications.
- Supports two comparison points during each counting period for interrupts and external events.
- Array of muxes with shared inputs, configurable for routing shared inputs to outputs.
- CCM_CLK1_P/CCM_CLK1_N: General purpose differential high-speed clock I/O.
- DCDC_PSWITCH: Connected to ground to bypass DCDC.
- RTC_XTALI/RTC_XTALO: Configurable as an RTC oscillator with a 32.768 kHz crystal.
- RTC_XTALI and RTC_XTALO should have minimal parasitic leakage to maintain amplifier bias and startup margin. They should bias to approximately 0.5 V.
- External low-frequency clocks can be fed into RTC_XTALI, with RTC_XTALO left unconnected or driven with a complementary signal. The clock logic level should not exceed VDD_SNVS_CAP, and frequency should be below 100 kHz.
- For systems not requiring high accuracy, an internal low-frequency ring oscillator can be used, connecting RTC_XTALI to GND and leaving RTC_XTALO unconnected.
- A 24.0 MHz crystal should be connected between XTALI and XTALO, with a maximum drive level of 250 µW and an ESR of 80 Ω recommended. An external 24 MHz oscillator can replace the crystal if available.
- JTAG interface does not require external resistors, but if used, they must follow on-chip configurations. JTAG_MOD should be connected to GND for normal operation.
- NC signals should be disconnected by the user.
- POR_B is a cold reset input that resets all modules and logic in the IC.
- ONOFF button configurations include debounce, off to on time, and max time-out settings.
- TEST_MODE is for factory use and should be tied to GND.
- WAKEUP is a GPIO powered by SNVS domain power supply, configurable as a wakeup source.
- Absolute maximum ratings are provided, with caution against exceeding these to avoid permanent damage.
- Operating ranges detail the voltage and temperature conditions for various modes, including Run, IDLE, SUSPEND, and SNVS modes.
- External clock sources include RTC_XTALI for low-frequency functions and XTALI for the main system clock, with specific frequency requirements outlined.
- Maximum supply currents are detailed for various power rails under specific conditions.
- Low power mode supply currents and USB PHY current consumption are specified for different operational states.
The document outlines various power modes for the i.MX RT1064 processors, detailing the power consumption in each mode. In the Run Mode, the total power consumption is 4.84 mW with specific current draws from DCDC_IN, VDD_HIGH_IN, and VDD_SNVS_IN. In Suspend Mode (DSM), power consumption drops to 0.789 mW, with LDO_2P5 and LDO_1P1 shut off, and the CPU in Power Gate mode. The SNVS (RTC) Mode maintains only the 32 kHz RTC alive, consuming 0.066 mW.
In power down mode, the USB PHY consumes minimal current, with VDD_USB_CAP at 5.1 μA, VDD_HIGH_CAP at 1.7 μA, and NVCC_PLL at less than 0.5 μA.
The document emphasizes the importance of adhering to power-up and power-down sequences to prevent excessive current, boot failures, or processor damage. Key points include ensuring VDD_SNVS_IN is powered before other supplies and managing the POR_B signal correctly.
The document describes various LDO regulators, including LDO_1P1, LDO_2P5, and LDO_USB, each with specific voltage ranges and functionalities. These regulators are crucial for powering internal components like USB PHY and PLLs, with features like programmable brown-out detectors and current limiting.
The DCDC converter operates in power-save mode under low load conditions and includes protection features like over-current and over-voltage protection.
Details are provided for Audio/Video, System, Ethernet, USB, and Arm PLLs, including clock output ranges and lock times.
The OSC24M and OSC32K oscillators are described, with the latter capable of switching to a backup battery when VDD_HIGH_IN is unavailable.
The document includes DC parameters for various I/O types, emphasizing the importance of maintaining voltage levels within specified limits to prevent device damage.
- High-Level Input Voltage (VIH): Must be 0.7 x NVCC_XXXX V.
- Low-Level Input Voltage (VIL): Must be 0 to 0.3 x NVCC_XXXX V.
- Input Hysteresis: 250 mV for both 1.8V and 3.3V NVCC_XXXX.
- Hysteresis of 250 mV is guaranteed when enabled.
- Threshold voltages (VTH+ and VTH-) are 0.5 x NVCC_XXXX mV.
- Various configurations with resistances of 22kΩ, 47kΩ, and 100kΩ, affecting current draw based on input voltage.
- Complies with TIA/EIA 644-A standard.
- Output Differential Voltage (VOD): 250-450 mV.
- Output High Voltage (VOH): 1.25-1.6 V.
- Output Low Voltage (VOL): 0.9-1.25 V.
- Transition times vary based on drive strength and load capacitance.
- Fast and slow modes are controlled via IOMUXC registers.
- Defined for single voltage GPIO with varying drive strengths.
- Impedance values range from 23Ω to 260Ω depending on NVCC_XXXX voltage.
- Reset and watchdog timing parameters are specified with diagrams for clarity.
- JTAG and debug trace timing specifications are detailed with minimum and maximum values.
- SEMC specifications for ASYNC and SYNC modes are provided.
- FlexSPI input/read timing is detailed for different modes and configurations.
The document outlines the FlexSPI input timing for SDR and DDR modes with various configurations of the RXCLKSRC register. Key parameters include the frequency of operation, setup and hold times, and the time delta between clock and data signals. For SDR mode, the frequency can reach up to 166 MHz, while DDR mode varies between 30 MHz and 166 MHz depending on the configuration.
The output timing for FlexSPI in SDR mode is detailed, with a maximum frequency of 166 MHz. Important parameters include the SCK clock period, output data valid and hold times, and chip select setup and hold times.
The document provides timing parameters for the CMOS Sensor Interface (CSI) in both gated and ungated clock modes, as well as for the LCD Controller (LCDIF). The CSI timing includes setup and hold times for data and sync signals, while the LCDIF timing focuses on pixel clock frequencies and data/control signal validity.
SAI/I2S and SPDIF timing specifications are provided for both master and slave modes. The SAI timing includes cycle times and setup/hold times for data and frame sync signals. SPDIF timing covers the modulation of Rx and Tx clocks.
The document details the DCDC electrical specifications, including input/output voltages, efficiency, and protection features. The 12-bit ADC characteristics are also covered, with operating conditions and input impedance details.
- Supply Current: Varies based on configurations of ADLPC and ADHSC, with values ranging from 350 µA to 750 µA.
- Sample and Conversion Cycles: Sample cycles range from 2 to 24 cycles, and conversion cycles range from 28 to 50 cycles depending on ADLSMP and ADSTS settings.
- Conversion Time: Ranges from 0.7 µs to 1.25 µs based on ADLSMP and ADSTS configurations.
- Errors: Total Unadjusted Error (TUE), Differential Non-Linearity (DNL), and Integral Non-Linearity (INL) are specified for 12, 10, and 8-bit modes.
- Supply Voltage: 3.0 to 3.6 V.
- Supply Current: High-speed mode at 347 µA and low-speed mode at 42 µA.
- Analog Input Voltage: Ranges from VSS to VDD.
- DAC Specifications: Includes integral and differential non-linearity with specified limits.
- LPSPI Timing: Provides synchronous serial bus operations with programmable attributes. Timing characteristics are detailed for both master and slave modes.
- LPI2C Timing: Describes timing parameters for different modes including standard, fast, and ultra-fast modes.
- SD/eMMC Timing: Includes specifications for single and dual data rate modes, with detailed timing diagrams and tables.
- MII Mode Timing: Describes receive and transmit signal timings with maximum frequency specifications.
- MII Asynchronous Inputs: The document outlines the timing for MII asynchronous inputs, including ENET_CRS and ENET_COL, with specific timing parameters detailed in Table 65.
- MII Transmit Signal Timing: Table 64 provides timing characteristics for ENET_TX_CLK related signals, with parameters like pulse width and data validity.
- RMII Mode Timing: RMII mode uses a 50 MHz reference clock, with timing parameters for signals like ENET_TX_EN and ENET_RX_DATA detailed in Table 67.
- The MII serial management channel timing is described, with the MDC frequency designed to be ≤2.5 MHz, but capable of functioning up to 15 MHz. Timing parameters are listed in Table 66.
- The USB PHY complies with USB 2.0 OTG specifications, with amendments for short circuit withstand, pull-up/down resistors, and suspend current limits.
- PWM Characteristics: The PWM clock frequency is specified up to 150 MHz.
- Quad Timer Timing: Timing parameters for quad timers are provided in Table 69, with details on input and output periods.
- Flash Parameters: Operating ranges for on-chip flash power supply are specified in Table 70.
- Boot Mode Configuration: Detailed information on boot mode pins and device interfaces is provided, with tables listing configurations for NAND, NOR, FlexSPI, SD, SPI, and UART boot modes.
- Details on the 10 x 10 mm package, including contact assignments and mechanical drawings, are provided. Tables 83 and 84 list supply and functional contact assignments.
Catalog excerpts
NXP Semiconductors Data Sheet: Technical Data i.MX RT1064 Crossover Processors for Industrial Products Package Information Plastic Package 196-pin MAPBGA, 10 x 10 mm, 0.65 mm pitch 196-pin MAPBGA, 12 x 12 mm, 0.8 mm pitch Ordering Information See Table 1 on page 6 The i.MX RT1064 is a new processor family featuring NXP’s advanced implementation of the Arm Cortex®-M7 core, which operates at speeds up to 528 MHz to provide high CPU performance and best real-time response. The i.MX RT1064 processor has 4 MB on chip Flash and 1 MB on-chip RAM. 512 KB SRAM can be flexibly configured as TCM or general-purpose on-chip RAM, while the other 512 KB SRAM is general-purpose on-chip RAM. The i.MX RT1064 integrates advanced power management module with DCDC and LDO that reduces complexity of external power supply and simplifies power sequencing. The i.MX RT1064 also provides various memory interfaces, including SDRAM, RAW NAND FLASH, NOR FLASH, SD/eMMC, Quad SPI, and a wide range of other interfaces for connecting peripherals, such as WLAN, Bluetooth™, GPS, displays, and camera sensors. The i.MX RT1064 has rich audio and video features, including LCD display, basic 2D graphics, camera interface, SPDIF, and I2S audio NXP reserves the right to change the production detail specifications as may be required to permit improvements in the design of its products. 1. i.MX RT1064 Introduction . . . . . . . . . . . . . . . . . . . . . . . . 1 1.1. Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1.2. Ordering information . . . . . . . . . . . . . . . . . . . . . . . 6 2. Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3. Modules List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.1. Special signal considerations . . . . . . . . . . . . . . . 16 3.2. Recommended connections for unused analog interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4. Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 19 4.1. Chip-Level conditions . . . . . . . . . . . . . . . . . . . . . 19 4.2. System power and clocks . . . . . . . . . . . . . . . . . . 25 4.3. I/O parameters . . . . . . . . . . . . . . . . . . . . . . . . . . 30 4.4. System modules . . . . . . . . . . . . . . . . . . . . . . . . . 36 4.5. External memory interface . . . . . . . . . . . . . . . . . 41 4.6. Display and graphics . . . . . . . . . . . . . . . . . . . . . . 51 4.7. Audio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 4.8. Analog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 4.9. Communication interfaces . . . . . . . . . . . . . . . . . . 64 4.10. Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 5. Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 6. Boot mode configuration . . . . . . . . . . . . . . . . . . . . . . . . 80 6.1. Boot mode configuration pins . . . . . . . . . . . . . . . 80 6.2. Boot device interface allocation . . . . . . . . . . . . . . 80 7. Package information and contact assignments . . . . . . . 85 7.1. 10 x 10 mm package information . . . . . . . . . . . . 85 7.2. 12 x 12 mm package information . . . . . . . . . . . . 97 8. Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
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i.MX RT1064 Introduction interface. The i.MX RT1064 has analog interfaces, such as ADC, ACMP, and TSC. The i.MX RT1064 is specifically useful for applications such as: • Industrial Human Machine Interfaces (HMI) • Motor Control • Home Appliance 1.1 Features The i.MX RT1064 processors are based on Arm Cortex-M7 MPCore™ Platform, which has the following features: • Supports single Arm Cortex-M7 MPCore with: — 32 KB L1 Instruction Cache — 32 KB L1 Data Cache — Full featured Floating Point Unit (FPU) with support of the VFPv5 architecture — Support the Armv7-M Thumb instruction set • Integrated MPU,...
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— Four Periodical Interrupt Timers (PIT) - Generic 32-bit resolution timer - Periodical interrupt generation — Four Quad Timers (QTimer) - 4-channel generic 16-bit resolution timer for each - Each support standard capture and compare operation - Quadrature decoder integrated — Four FlexPWMs - Up to 8 individual PWM channels per each - 16-bit resolution PWM suitable for Motor Control applications — Four Quadrature Encoder/Decoders Each i.MX RT1064 processor enables the following interfaces to external devices (some of them are muxed and not available simultaneously): • Display Interface: — Parallel...
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i.MX RT1064 Introduction — Two Ultra Secure Digital Host Controller (uSDHC) interfaces - MMC 4.5 compliance with HS200 support up to 200 MB/sec - SD/SDIO 3.0 compliance with 200 MHz SDR signaling to support up to 100 MB/sec - Support for SDXC (extended capacity) — Two 10/100M Ethernet controller with support for IEEE1588 — Eight universal asynchronous receiver/transmitter (UARTs) modules — Four I2C modules — Four SPI modules — Two FlexCAN modules — FlexCAN (with Flexible Data-Rate supported) — Three FlexIO modules • GPIO and Pin Multiplexing: — General-purpose input/output (GPIO) modules with...
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• Secure Non-Volatile Storage (SNVS) — Secure real-time clock (RTC) — Zero Master Key (ZMK) • Secure JTAG Controller (SJC) NOTE The actual feature set depends on the part numbers as described in Table 1. Functions such as display and camera interfaces, connectivity interfaces, and security features are not offered on all derivatives. i.MX RT1064 Crossover Processors for Industrial Products, Rev. 0, 05/2019
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i.MX RT1064 Crossover Processors for Industrial Products, Rev. 0, 05/2019
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Figure 1 describes the part number nomenclature so that characteristics of a specific part number can be identified (for example, cores, frequency, temperature grade, fuse options, and silicon revision). The primary characteristic which describes which data sheet applies to a specific part is the temperature grade (junction) field. Ensure to have the proper data sheet for specific part by verifying the temperature grade (junction) field and matching it to the proper data sheet. If there are any questions, visit the web page nxp.com/IMX-RT_SERIES or contact an NXP representative for details. Prototype...
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- Acceleration sensor
- Pressure probe
- Signal amplifying integrated circuit
- Multipole switch
- Single-axis accelerometer
- Triaxial acceleration sensor
- Power amplifying integrated circuit
- Compact accelerometer
- Precision temperature transducer
- Transistor module
- Touch switch
- Radio receiver
- Absolute pressure sensor
- Sensitive element pressure sensor
- Industrial accelerometer
- MEMS accelerometer
- Digital temperature sensor