SOLOMON SYSTECH SEMICONDUCTOR TECHNICAL DATA This document contains information on a new product. Specifications and information herein are subject to change without notice. Copyright © 2008 Solomon Systech Limited SYSTECH

Solomon Systech

Solomon Systech

Solomon Systech

Solomon Systech

The SSD1305 is a CMOS OLED/PLED driver with controller for organic/polymer light emitting diode dotmatrix graphic display system. It consists of 132 segments and 64 commons that can support a maximum display resolution of 132x64. There are 4-color selections to support monochrome or area color OLED/PLED. This IC is designed for Common Cathode type OLED panel. The SSD1305 embeds with contrast control, display RAM and oscillator, which reduces the number of external components and power consumption. It has 256-step brightness control and separate power for I/O interface logic. It is suitable for...

Figure 4-1 : SSD1305 Block Diagram Solomon Systech

Alignment marks (For details dimension please see p.9) Solomon Systech

Figure 5-2 : SSD1305Z Alignment Marks Dimension Solomon Systech

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SSD1305T6R1 pin assignment Figure 6-1 : SSD1305T6R1 Pin Assignment Solomon Systech

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Key: I = Input, O =Output, IO = Bi-directional (input/output), P = Power pin Solomon Systech

Table 7-2 : MCU Bus Interface Pin Selection Solomon Systech

SSD1305 MCU interface consist of 8 data pins and 5 control pins. The pin assignment at different interface mode is summarized in Table 8-1. Different MCU mode can be set by hardware selection on BS[2:0] pins (please refer to Table 7-2 for BS[2:0] setting). Table 8-1 : MCU interface assignment under different bus interface mode (1) i stands for falling edge of signal H stands for HIGH in signal L stands for LOW in signal In order to match the operating frequency of display RAM with that of the microprocessor, some pipeline processing is internally performed which requires the insertion of a dummy...

Figure 8-1 : Data read back procedure - insertion of dummy read R/W# Write column address Dummy read The parallel interface consists of 8 bi-directional data pins (D[7:0]), RD#, WR#, D/C# and CS#. A LOW in D/C# indicates COMMAND read/write and HIGH in D/C# indicates DATA read/write. A rising edge of RD# input serves as a data READ latch signal while CS# is kept LOW. A rising edge of WR# input serves as a data/command WRITE latch signal while CS# is kept LOW. Figure 8-2 : Example of Write procedure in 8080 parallel interface mode CS# WR# D[7:0] Figure 8-3 : Example of Read procedure in 8080 parallel...

Table 8-3 : Control pins of 8080 interface (Form 1) (1) t stands for rising edge of signal (2) H stands for HIGH in signal (4) Refer to Figure 13-3 for Form 2 8080-Series MPU Parallel Interface Timing Characteristics In order to match the operating frequency of display RAM with that of the microprocessor, some pipeline processing is internally performed which requires the insertion of a dummy read before the first actual display data read. This is shown in Figure 8-4. Dummy read Read 1st data Read 2nd data Solomon Systech

The serial interface consists of serial clock SCLK, serial data SDIN, D/C#, CS#. In SPI mode, DO acts as SCLK, D1 acts as SDIN. For the unused data pins, D2 should be left open. The pins from D3 to D7, E and R/W# can be connected to an external ground. Table 8-5 : Control pins of Serial interface (1) t stands for rising edge of signal (2) H stands for HIGH in signal SDIN is shifted into an 8-bit shift register on every rising edge of SCLK in the order of D7, D6, ... D0. D/C# is sampled on every eighth clock and the data byte in the shift register is written to the Graphic Display Data RAM (GDDRAM)...

SDA acts as a communication channel between the transmitter and the receiver. The data and the acknowledgement are sent through the SDA. It should be noticed that the ITO track resistance and the pulled-up resistance at “SDA” pin becomes a voltage potential divider. As a result, the acknowledgement would not be possible to attain a valid logic 0 level in “SDA”. “SDAin” and “SDAOUT” are tied together and serve as SDA. The “SDAIN” pin must be connected to act as SDA. The “SDAOUT” pin may be disconnected. When “SDAOUT” pin is disconnected, the acknowledgement signal will be ignored in the I2C-bus....

1) The master device initiates the data communication by a start condition. The definition of the start condition is shown in Figure 8-7. The start condition is established by pulling the SDA from HIGH to LOW while the SCL stays HIGH. 2) The slave address is following the start condition for recognition use. For the SSD1305, the slave address is either “b0111100” or “b0111101” by changing the SA0 to LOW or HIGH (D/C pin acts as SA0). 3) The write mode is established by setting the R/W# bit to logic “0”. 4) An acknowledgement signal will be generated after receiving one byte of data, including...

Figure 8-8 : Definition of the acknowledgement condition DATA OUTPUT BY TRANSMITTER DATA OUTPUT BY RECEIVER Clock pulse for acknowledgement Please be noted that the transmission of the data bit has some limitations. 1. The data bit, which is transmitted during each SCL pulse, must keep at a stable state within the “HIGH” period of the clock pulse. Please refer to the Figure 8-9 for graphical representations. Except in start or stop conditions, the data line can be switched only when the SCL is LOW. 2. Both the data line (SDA) and the clock line (SCL) should be pulled up by external resistors....

Oscillator Circuit and Display Time Generator Figure 8-10 : Oscillator Circuit and Display Time Generator Internal Oscillator Fosc M U X DCLK Display Clock This module is an on-chip LOW power RC oscillator circuitry. The operation clock (CLK) can be generated either from internal oscillator or external source CL pin. This selection is done by CLS pin. If CLS pin is pulled HIGH, internal oscillator is chosen and CL should be connected to VSS. Pulling CLS pin LOW disables internal oscillator and external clock must be connected to CL pins for proper operation. When the internal oscillator is selected,...