LONTIUM SEMICONDUCTOR CORPORATION ClearEdge Technology LT6911C HDMI1.4/DP++ to Dual-port MIPI DSI/CSI/LVDS with Audio Datasheet We produce mixed-signal products for a better digital world!

■ Compliant with the HDM11.4 specification with TMDS data rates up to 3.4Gbps per channel ■ Adaptive receiver equalization for PCB, cable and connector losses • Dual-mode DispalyPort Receiver ■ Compliant with DisplayPort Dual-mode spec 1.1(DP++)with 4K30Hz HDMI support ■ Adaptive receiver equalization to compensate PCB and/or connector losses ■ Integrated 500 termination resistors for AC coupled differential inputs ■ Low Intra-pair and I nter-pair skews ■ Support DisplayPort all 4 levels of output • Single/Dual-Port MIPI® DSI/CSIT ransmitter ■ 1 Clock Lane, and 1 ~4 Configurable Data Lanes per...

Figure 3.1 Application Diagrams 4. Ordering Information Table 4.1 Ordering Information Part Number Operating Temperature Range Packing Method We produce mixed-signal products for a better digital world!

We produce mixed-signal products for a better digital world!

We produce mixed-signal products for a better digital world!

6. Pinning Information 6.1 Pin Configuration Figure 6.1.1 LT6911C (QFN64) Pin Assignment (Top View) We produce mixed-signal products for a better digital world!

7. Function Description 7.1 Function Block Diagram Figure 7.1.1 Function Block Diagram We produce mixed-signal products for a better digital world!

8.1 Absolute Maximum Conditions Table 8.1.1 Absolute Maximum Conditions

When only VCC33 active, the I2C bus(CSDA/CSCL) follow the voltage of the pin SLEEP 33 Note: In order to avoid the I2C error (3), you can select the second reset sequence(2). Figure 8.6.1 Power-up and Reset Sequence

9. Package Information The LT6911C is packaged in a 64-lead QFN package with ePad. The ePad needs to be soldered to the PCB. The information in the following paragraphs is provided for applications which solder the ePad to the PCB. The ePad must not be electrically connected to any other voltage level except ground (GND). A clearance of at least 0.25mm should be designed on the PCB between the edge of the ePad and the inner edges of the lead pads to avoid any electrical shorts. 9.1 Package Dimensions Figure 9.1.1 is the package dimensions for the date code beginning with GT. Figure 9.1.2 is the...

JUUUUUUUUUUUUIJU ISE=lcl SEATING PLANE SIDE VIEW TOTAL THICKNESS LEAD WIDTH BODY SIZE LEAD PITCH LEAD LENGTH 2X0PLANARITY APPLIES TO LEADS, CORNER LEADS AND DIE ATTACH PAD: 3, BAN TO USE THE LEVEL 1 ENVIRONMENT—RELATED SUBSTANCES OF JCET PRESCRIBING; BOTTOM VIEW Figure 9.1.2 Package Dimensions (JC)

We produce mixed-signal products for a better digital world!

STACKING DETAIL TRAY STACKING DETAIL SECTION “B-Bm Vmzs/t) SUP LOCK DETAIL VACUUM CELL (scx&a/j) (SCALES/!) S£ ■ JH)EC PACKING TRAY FOR QFN 7iX75X0.75mm(X7M) 9K: 46-00007-021 We produce mixed-signal products for a better digital world! 19

Figure 9.2.1 Packing Dimensions We produce mixed-signal products for a better digital world!

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