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EK79202D

Product catalog summary

General Description: The EK79202D is an integrated solution for small to medium-sized α-Si TFT-LCD panels, featuring a 2052 channel source driver and a timing controller. It supports MIPI/LVDS interfaces and allows function settings through R/W SPI/3-wire serial interface.

Features: This single-chip solution supports WXGA a-Si type LCD displays with resolutions like 1366 RGB x 768 and 1280 RGB x 800. It includes a 2052 channel source driver, timing controller, programmable gamma correction, and OTP memory for initialization settings. Interfaces include MIPI DSI and LVDS, with a built-in VCOM generator and enhanced BIST pattern.

Chip Function Block Diagram: Key components include MIPI/LVDS Decoder, Power Converter, Regulator, SPI, OTP, Gamma, Timing Controller, Source Driver, and GOA (Level Shift).

Pad Arrangement: Details on the pad arrangement for signal and power pads necessary for operation are provided.

Application Diagrams: Application diagrams for different panel configurations, including GIP and Cascade applications, are included.

Pin Function Description: Detailed descriptions of pin functions, definitions, and wiring resistance values are provided.

Register Command Format: I2C and SPI formats for register command sequences are outlined.

Video Interface: Details on MIPI and LVDS interfaces, including timing tables and power sequences, are provided.

Power Sequence and External Power Circuit: Information on power generation, power-on sequence, and application power circuits is included.

Function Description: Descriptions of the BIST pattern and gamma correction resistances, including input data and output voltage relationships, are provided.

DC and AC Characteristics: Absolute maximum ratings, typical operating conditions, and electrical characteristics for both DC and AC modes are detailed.

Chip Outline Dimension: Dimensions and alignment marks for the chip are detailed.

Overview: This document provides technical specifications and configurations for the EK79202D, including pin configurations, input/output settings, and operational modes.

1. LVDS Data and Clock Lane Mapping: LVDS data and clock lane swapping selection based on LNSW[1:0] settings is outlined, affecting data lane sequences.

2. Panel Resolution Settings: RES[2:0] pins determine panel resolution, with specific settings for different resolutions. LVDS mode settings are for resolution functions, with additional settings dependent on ZIGZAG and ZTYPE pin selections.

3. Pin Descriptions: Detailed descriptions for various pins, including DIR, REV, and OP_DRV, are provided, explaining each pin's function, default states, and operational modes.

4. Power Supply and Ground Connections: Power supply requirements for analog and I/O circuits, including VDD, VDDIO, and VSS, are specified, along with connections for stabilizing capacitors.

5. I2C Interface and Register Command Format: The I2C interface for setting internal registers is explained, including the I2C-bus protocol and register writing sequence.

6. Additional Features: Features include standby mode, BIST pattern selection, dithering function control, GIP level shift selection, and inversion mode settings.

7. Application and Configuration Notes: Notes on application block diagrams, chip positioning, and the impact of different settings on display output and performance are included.

Vertical and Horizontal Timing Specifications: Vertical display area is 768 H, with VSYNC period time ranging from 778 to 845 H. VSYNC blanking is specified between 10 and 77 H, with a note that blanking settings must be even numbers.

Gate Output Timing: Parameters for gate output timing, including pulse widths and time intervals between signals such as STV, CKV, and OEV, are provided.

Power Sequence and External Power Circuit: Various voltage requirements for components like VDD, VSP, VSN, VGMP, and VGMN are listed, with detailed power on and off sequences.

Function Description: BIST pattern mode for testing and debugging, including color patterns and grayscale tests, is described.

Gamma Correction: Gamma correction using a resistor stream and a 64-to-1 selector to adjust voltages is explained, with specific gamma corrected reference voltages for positive and negative polarity outputs.

DC Characteristics: Absolute maximum ratings and typical operating conditions for various parameters, including I/O voltage, power input, and operating/storage temperatures, are provided.

LVDS and MIPI Characteristics: LVDS DC and AC electrical characteristics, including differential input thresholds, impedance, and current consumption, are specified. MIPI characteristics for high-speed and low-power modes are also detailed.

AC Characteristics: AC electrical characteristics for LVDS mode, source output timing, and serial interface characteristics are provided.

Chip Outline Dimension: Detailed dimensions and coordinates for various components of the chip, including alignment marks and pad coordinates, are provided.

Alignment Marks: Alignment marks with dimensions of 80um by 10um, located on both the right and left sides of the chip, are specified.

Pad Coordinates: A comprehensive list of pad names along with their respective X and Y axis coordinates is provided.

Key Parameters: Critical parameters such as bump height and alignment mark dimensions are highlighted.

Document Overview: This document is a preliminary technical specification for the EK79202D, detailing pin configurations, pad names, and their respective coordinates on the X and Y axes.

Key Sections:

Pin Configuration: Lists pins and dummy pads with their respective X and Y coordinates.
Revision History: Provides a timeline of updates made to the document, including notable revisions.

Critical Information:

Specifications: Specifies the layout of pins and pads for the design and integration of the EK79202D.
Revisions: Latest revision (0.3) includes modifications to the LNSW definition.

Conclusion: The document serves as a comprehensive guide for engineers and designers working with the EK79202D, providing detailed layout information and a history of updates to ensure accurate implementation and integration.

Catalog excerpts

2052CH Source Driver with TCON MIPI/LVDS Interface fitipower integrated technology Inc.

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The EK79202 is a highly integrated solution for small size to middle size a-Si TFT-LCD panels. This chip integrates 2052 channel source driver a timing controller for color TFT LCD panel. The chip support MIPI/LVDS interface. And support the function setting through R/W SPI/3-wie serial interface • Single chip solution for a WXGA a-Si type LCD display • Integrate 2052 channel source driver and timing controller • Display Resolution : • System Interfaces: Integrate 2052 channel source driver and timing controller Support for Programming Gamr OTP memory to store initializ Support SPI/I2C interface...

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Preliminary EK79202D 3. Chip Function Block Diagram VGMP VGMN MIPI/LVDS Decoder Source Driver POWER converter Timing Controller VCL VGMP VGMN VGL_REG VGH_REG VDD_15V VDD_15V_IF

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EK79202 Left side (face up) EK79202 Right side (face up)

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Preliminary EK79202D 5. Application Diagram with Panel 5.1 GIP Application_1366RGBx768 (Normal Dual Gate Driving) Driving method : Cascade=0 Data1 EK79202 IC Bump side down (2052CH) Disable channel -

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Preliminary EK79202D 5.2 GIP Application_1280RGBx800 (Normal Dual Gate Driving) Driving method : Cascade=0 Data1 EK79202 IC Bump side down (2052CH)

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Preliminary EK79202D 5.3 GIP Application_1280RGBx800 ((Dual Gate+Zigzag Driving) Driving method : Cascade=0 Data1 EK79202 IC Bump side down (2052CH)

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Preliminary EK79202D 5.4 GIP Application_1024RGBx768 (Normal Dual Gate Driving) Driving method : Cascade=0 Data1 EK79202 IC Bump side down (2052CH)

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Preliminary EK79202D 5.5 Cascade Application1_1366RGBx768 ( on MIPI/LVDS mode ) Driving method : Cascade=1 / Zigzag=0 Data1 EK79202 IC Bump side down SDLOC=H : chip on left side Scan direction EK79202 IC Bump side down SDLOC=L : chip on right side

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Preliminary EK79202D 5.6 Cascade Application2_1366RGBx768 ( on MIPI/LVDS mode ) Driving method : Cascade=1 / Zigzag=1 / ZTYPE=0 Data1 Scan direction EK79202 IC Bump side down SDLOC=H : chip on left side EK79202 IC Bump side down SDLOC=L : chip on right side

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Preliminary EK79202D 5.7 Cascade Application3_1366RGBx768 ( on MIPI/LVDS mode ) Driving method : Cascade=1 / Zigzag=1 / ZTYPE=1 Data1 Scan direction EK79202 IC Bump side down SDLOC=H : chip on left side EK79202 IC Bump side down SDLOC=L : chip on right side

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Preliminary EK79202D 5.8 Cascade Application4_1280RGBx800 ( on MIPI/LVDS mode ) Driving method : Cascade=1 / Zigzag=0 Data1 EK79202 IC Bump side down SDLOC=H : chip on left side Scan direction EK79202 IC Bump side down SDLOC=L : chip on right side

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Preliminary EK79202D 5.9 Cascade Application5_1280RGBx800 ( on MIPI/LVDS mode ) Driving method : Cascade=1 / Zigzag=1 / ZTYPE=0 Data1 DIR=H Scan direction EK79202 IC Bump side down SDLOC=H : chip on left side EK79202 IC Bump side down SDLOC=L : chip on right side

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Preliminary EK79202D 5.10 Cascade Application6_1280RGBx800 ( on MIPI/LVDS mode ) Driving method : Cascade=1 / Zigzag=1 / ZTYPE=1 Data1 DIR=H Scan direction EK79202 IC Bump side down SDLOC=H : chip on left side EK79202 IC Bump side down SDLOC=L : chip on right side

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Preliminary EK79202D 5.11 Dual gate & GOA Application note Data1 Backward direction Forward directin Forward directin Backward direction EK79202 IC Bump side down (2052CH) Backward direction Forward direction

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Preliminary EK79202D 5.12 Normal Dual gate & GOA Application note Data1 Backward direction Forward directin Forward directin Backward direction EK79202 IC Bump side down (2052CH) Backward direction Forward direction

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6. Pin Function Description 6.1 Pin define MIPI or LVDS data Input. Select by IFSEL[1:0] pin MIPI/LVDS clock Input. \Note: (1) LVDS data lane sequence are used when IFSEL[1:0]=[0:1] (2) Refer to Note2 LVDS polarity selection pins. Normally pull low. LVDS mode : RES[2:0] setting only for resolution function, Zigzag panel structure setting depend on ZIGZAG & ZTYPE pin selection(Select by pin or OTP) Vertical display line set by internal OTP._

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Description The shift direction of device internal shift register is controlled by this as shown below : Normally pull high DIR Function H OUT[0,1,2]‧‧‧OUT[2049,2050,2051] L OUT[2049,2050,2051]‧‧‧OUT[0,1,2] Cascade=H + RES[2:0]=1366x768 only support DIR=H Controls whether the data of D0~D2 are inverted or not, Normally pull low. When “REV”=1 these data will be inverted. EX. “00”→“ 3F”, “07”→“ 38”, “15”→“2A”, and so on. Source OP driving selection: OP_DRV[1:0] (VDDIO) DVCOM_WP (VDDIO) DVCOM_EN (VDDIO) Write protection for internal OTP. Normally High-Z DVCOM_WP Function H Enable write protect...

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Frame inverse or not select. Normally pull low

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LVBIT (VDDIO) Description 6-bit / 8-bit input select for LVDS mode. Normally pull high. (only for LVDS) LVBIT Function H 8-bit (default) L 6-bit Dithering function enable control. Normally pull low In LVDS 6-bit mode, IC don’t care DITHER and HFRC setting. DITHER_EN (VDDIO) HFRC_EN (VDDIO) H-FRC selection. Normally pull low HFRC = H : H-FRC enable If “DITHER”=”L”,disable dithering function(HFRC and FRC disable) Command interface selection. Normally pull high. CMD_SEL Function H I2C (default) L 3-Wire 3-wire/I2C command can’t receive at the same time. UPDN (VDDIO) Setting flexible GOA scan function....

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Preliminary EK79202D Panel driver output Source output mapping with different resolution.2051 Source output control by RES[2:0] pin define On Dual gate mode : CAS=0 are used for Panel gate control signals. If not used, let it open. anel gate control signals. If not used, let it open. r supply for analog circuit. VDD=2.3V to 3.6V ;rnal power supply for logic circuits. Connect to a stabilizing capacitor. Internal power supply for LVDS circuits. Connect to a stabilizing capacitor. Interface and I/O power supply for the LVDS power regulator circuits. VDDIO=2.3V to 3.6V. . GND for the internal logic....

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EK79202D

EK79202D

Catalog excerpts

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