ML4039B 4-Lane | 200G BERT | 1.25 – 29 GBd | NRZ & PAM4 4 Differential Error Detectors with CDR | 4 Differential Pulse Pattern Generators | PRBS31Q, SSPRQ & Custom Pattern | Adaptive FFE on receivers | Pre and Post Emphasis on TX | Real FEC analysis With the accelerated growth of hyperscale datacenters, performance demands of Ethernet networks are increasing exponentially. As customer expectations for high-speed data throughput are at an all-time high, Bit Error Rate Testers (BERTs) have become a cornerstone for physical layer testing. Use cases range from qualifying bit transmission for fiber optic and copper-wire digital data transmission lines to testing signal integrity. A BERT generates a sequence of bits through a communication channel and the received bits are then compared against the transmitted bits. A Bit Error Ratio (BER) quantifies the full end-to-end performance of a connectivity system and assures communication reliability. Additionally. This BERT supports the increasingly crucial real hardware FEC analysis to understand how your DUT will behave in a real data center environment. The ML4039B is a 4-lane 200G BERT ideal for the testing of active semiconductor implementations. Some of its highlighted features include 4 differential error detectors and pulse pattern generators, custom pattern generation in addition to PRBS and SSPRQ, adaptive receiver FFE, transmitter pre/post-emphasis and progressive troubleshooting capabilities.

The ML4039B is a fully featured 200G Bit Error Rate Tester. It has instrument-grade 2.92 mm coaxial connectors and covers a wide range of bitrates between 1.25 and 29 Gigabaud, while supporting both NRZ and PAM4 encoding schemes. The GUI supports individual control of each TX level, equalization, eye balance, and pattern selection. The user may also inject error sequences into the stream. Th e receiver features CTLE and FFE equalization that, in combination with TX FFE, compensates for up to 30 dB of loss at Nyquist. It also enables advanced debug capabilities by showing separate LSB and MSB...

• High-value, instrument-grade BERT optimized for high-speed data analysis of 100G/200G devices • Wide range of bitrate coverage enables PHY testing for Ethernet, HDMI 2, USB 3.1, PCIe, Fiber-Channel and more • Ability to tune the bit rate in very fine steps to facilitate finding the locking margin • Supports PRBS13Q/15Q/31Q and user-defined patterns • API library, sample code and Python wrapper • Production testing of modules, cables and optoelectrical ICs • Benchtop testing for functional and SI validation • Transceiver functionality validation testing Using ThunderBERT GUI, both instant and...

Figure 3: ML4039B Block Diagram ThunderBERT GUI The ThunderBERT GUI is highly intuitive and responsive, supporting a variety of tests and measurements on the ML4039B platform. Please refer to the ThunderBERT User’s Guide for detailed operational instructions. Figure 5: Main GUI multilaneinc.com Figure 4: ML4039B front view

multi Lane^Electrical Specifications Parameter 1 - CDR Clock is available on the revision E of the ML4039B Hardware multilaneinc.com

multi Lane^ Mechanical Dimensions The ML4039B is a benchtop instrument which also fits in a 19-inch 2U rack. Two ML4039B arranged side by side take up a single 2-RU slot in a rack. MultiLane also supplies the needed brackets. Please contact us at [email protected].