Stand-Alone 10/100 Ethernet Controller with SPI or Parallel Interface
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㦠2010 Microchip Technology Inc. DS39935C ENC424J600/624J600 Data Sheet Stand-Alone 10/100 Ethernet Controller with SPI or Parallel Interface

DS39935C-page ii 㦠2010 Microchip Technology Inc. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability...

„¶ 2010 Microchip Technology Inc. DS39935C-page 1 ENC424J600/624J600 • IEEE 802.3™ Compliant Fast Ethernet Controller • Integrated MAC and 10/100Base-T PHY • Hardware Security Acceleration Engines • 24-Kbyte Transmit/Receive Packet Buffer SRAM • Supports one 10/100Base-T Port with Automatic Polarity Detection and Correction • Supports Auto-Negotiation • Support for Pause Control Frames, including Automatic Transmit and Receive Flow Control • Supports Half and Full-Duplex Operation • Programmable Automatic Retransmit on Collision • Programmable Padding and CRC Generation • Programmable...

„¶ 2010 Microchip Technology Inc. DS39935C-page 5 ENC424J600/624J600 1.0 DEVICE OVERVIEW This document contains device-specific information for the following devices: • ENC424J600 • ENC624J600 The ENC424J600 and ENC624J600 are stand-alone, Fast Ethernet controllers with an industry standard Serial Peripheral Interface (SPI) or a flexible parallel interface. They are designed to serve as an Ethernet network interface for any microcontroller equipped with SPI or a standard parallel port. ENC424J600/624J600 devices meet all of the IEEE 802.3 specifications applicable to 10Base-T and 100Base-TX...

ENC424J600/624J600 DS39935C-page 6 㦠2010 Microchip Technology Inc. FIGURE 1-1: ENC424J600/624J600 BLOCK DIAGRAM 24 Kbytes DMA and Checksum TX Control RX Control Arbiter Flow Control Control Host Interface Registers 25 MHz Power-on PHY MII Interface MIIM Interface TPOUT+ TPOUTTPIN+ TPINTX RX RBIAS OSC1 OSC2 Control Logic CS/CS SI/RD/RW SO SCK/AL INT LEDA LEDB CLKOUT VCAP RX Filter MAC m3 m1 SRAM Note 1: A<14:0>, AD15, WRL/B0SEL, WRH/B1SEL and PSPCFG<4:1> are available on 64-pin devices only. PSPCFG0 is available on 44-pin devices only. Reset Oscillator I/O Interface AD<15:0>(1) A<14:0>(1)...

„¶ 2010 Microchip Technology Inc. DS39935C-page 7 ENC424J600/624J600 TABLE 1-2: ENC424J600/624J600 PINOUT DESCRIPTIONS Pin Name Pin Number Pin Type Input Buffer Description 44-Pin 64-Pin AD0 38 53 I/O CMOS PSP Multiplexed Address Input and/or Bidirectional AD1 39 54 I/O CMOS Data Bus AD2 40 55 I/O CMOS AD3 41 56 I/O CMOS AD4 5 5 I/O CMOS AD5 6 6 I/O CMOS AD6 7 7 I/O CMOS AD7 8 8 I/O CMOS AD8 25 35 I/O CMOS AD9 26 36 I/O CMOS AD10 27 37 I/O CMOS AD11 28 38 I/O CMOS AD12 29 39 I/O CMOS AD13 30 40 I/O CMOS AD14 31 41 I/O CMOS AD15 — 42 I/O CMOS A0 — 57 I CMOS PSP Demultiplexed Address Input...

ENC424J600/624J600 DS39935C-page 8 „¶ 2010 Microchip Technology Inc. OSC1 3 3 I ANA 25 MHz Crystal Oscillator/Clock Input OSC2 2 2 O — 25 MHz Crystal Oscillator Output PSPCFG0 32 — I CMOS PSP Mode Select 0 PSPCFG1 — 45 I CMOS PSP Mode Select 1 PSPCFG2 — 17 I CMOS PSP Mode Select 2 PSPCFG3 — 18 I CMOS PSP Mode Select 3 PSPCFG4 — 52 I CMOS PSP Mode Select 4 RBIAS 11 16 I ANA PHY Bias (external resistor) Connection RD 36 51 I CMOS PSP Read Strobe RW 36 51 I CMOS PSP Combined Read/Write Signal SCK 37 52 I CMOS SPI Serial Clock Input SI 36 51 I CMOS SPI Serial Data Input (from Master) SO 35 50 O...

„¶ 2010 Microchip Technology Inc. DS39935C-page 9 ENC424J600/624J600 2.0 EXTERNAL CONNECTIONS 2.1 Oscillator ENC424J600/624J600 devices are designed to operate from a fixed 25 MHz clock input. This clock can be generated by an external CMOS clock oscillator or a parallel resonant, fundamental mode 25 MHz crystal attached to the OSC1 and OSC2 pins. Use of a crystal, rated for series resonant operation, will oscillate at an incorrect frequency. To comply with IEEE 802.3 Ethernet timing requirements, the clock must have no more than ±50 ppm of total error; avoid using resonators or clock...

ENC424J600/624J600 DS39935C-page 10 „¶ 2010 Microchip Technology Inc. 2.3 Voltage and Bias Pin 2.3.1 VDD AND VSS PINS To reduce on-die noise levels and provide for the high-current demands of Ethernet, there are many power pins on ENC424J600/624J600 devices: • VDD and VSS • VDDOSC and VSSOSC • VDDPLL and VSSPLL • VDDRX and VSSRX • VDDTX and VSSTX Each VDD and VSS pin pair above should have a 0.1 ƒÝF ceramic bypass capacitor placed as close to the pins as possible. For best EMI emission suppression, other smaller capacitors, such as 0.001 ƒÝF, should be placed immediately across VDDTX/VSSTX...

㦠2010 Microchip Technology Inc. DS39935C-page 11 ENC424J600/624J600 2.4 Ethernet Signal Pins and External Magnetics Typical applications for ENC424J600/624J600 devices require an Ethernet transformer module, and a few resistors and capacitors to implement a complete IEEE 802.3 compliant 10/100 Ethernet interface, as shown in Figure 2-5. The Ethernet transmit interface consists of two pins: TPOUT+ and TPOUT-. These pins implement a differential pair and a current-mode transmitter. To generate an Ethernet waveform, ordinary applications require the use of a 1:1 center tapped pulse...

ENC424J600/624J600 DS39935C-page 12 㦠2010 Microchip Technology Inc. 2.4.1 ADDITIONAL EMI AND LAYOUT CONSIDERATIONS To reduce EMI emissions, common-mode chokes are shown adjacent to the transformers on the cable (RJ-45) side. These chokes come standard in typical Ethernet transformer modules. Because the ENCX24J600 PHY uses a current-mode drive topology, the transmit choke must normally be located on the cable side of the transmit transformer. Orienting the magnetics such that the choke is on the PHY side of the transmit transformer usually results in a distorted, non-compliant transmit...