Mobile 4th Gen Intel® Core? Processor Family: Specification Update
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Mobile 4th Generation Intel® Core™ Processor Family, Mobile Intel® Pentium® Processor Family, and Mobile Intel® Celeron® Processor Family Specification Update Supporting 4th Generation Intel® Core™ Processor based on Mobile MProcessor and H-Processor Lines Supporting 4th Generation Intel® Core™ Processor based on Mobile UProcessor and Y-Processor Lines June 2014 Revision 012

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Specification Update

Specification Update

Revision History Revision 001 Description Initial Release. No Updates. Revision number added to Revision History to maintain consistency with NDA Specification Update numbering. Errata — Added D-0 stepping to errata summary table — Added HSM60-106 Updated Identification Information No Updates. Revision number added to Revision History to maintain consistency with NDA Specification Update numbering. Errata — Moved previous HSM106 to HSM116 — Added HSM106-115 and HSM117–125 Processor Identification — Updated Table 3, Processor Identification by Register Contents — Updated Table 4, 4th...

Preface This document is an update to the specifications contained in the Affected Documents table below. This document is a compilation of device and documentation errata, specification clarifications and changes. It is intended for hardware system manufacturers and software developers of applications, operating systems, or tools. Information types defined in Nomenclature are consolidated into the specification update and are no longer published in other documents. This document may also contain information that was not previously published. Affected Documents Document Title Generation...

Document Title 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes ACPI Specifications Document Number/ Location http://www.intel.com/ content/www/us/en/ processors/architectures-softwaredevelopermanuals.html Nomenclature Errata are design defects or errors. These may cause the processor behavior to deviate from published specifications. Hardware and software designed to be used with any given stepping must assume that all errata documented for that stepping are present on all devices. S-Spec Number is a five-digit code used to identify products. Products are...

Summary Tables of Changes The following tables indicate the errata, specification changes, specification clarifications, or documentation changes which apply to the processor. Intel may fix some of the errata in a future stepping of the component, and account for the other outstanding issues through documentation or specification changes as noted. These tables uses the following notations. Codes Used in Summary Tables Stepping X: Errata exists in the stepping indicated. Specification Change or Clarification that applies to this stepping. This erratum is fixed in listed stepping or...

Errata (Sheet 1 of 5) Steppings Number LBR, BTS, BTM May Report a Wrong Address when an Exception/ Interrupt Occurs in 64-bit Mode EFLAGS Discrepancy on Page Faults and on EPT-Induced VM Exits after a Translation Change MCi_Status Overflow Bit May Be Incorrectly Set on a Single Instance of a DTLB Error MONITOR or CLFLUSH on the Local XAPIC's Address Space Results in Hang An Uncorrectable Error Logged in IA32_CR_MC2_STATUS May also Result in a System Hang #GP on Segment Selector Descriptor that Straddles Canonical Boundary May Not Provide Correct Exception Error Code FREEZE_WHILE_SMM Does...

Errata (Sheet 2 of 5) Steppings Number Performance Monitor Counters May Produce Incorrect Results Performance Monitor UOPS_EXECUTED Event May Undercount MSR_PERF_STATUS May Report an Incorrect Core Voltage PCIe* Atomic Transactions From Two or More PCIe Controllers May Cause Starvation The Corrected Error Count Overflow Bit in IA32_ MC0_STATUS is Not Updated After a UC Error is Logged An AVX Gather Instruction That Causes an EPT Violation May Not Update Previous Elements LPDDR Memory May Report Incorrect Temperature PCIe* Host Bridge DID May Be Incorrect TSC May be Incorrect After a Deep...

Errata (Sheet 3 of 5) Steppings Number Processor May Not Enter Package C6 or Deeper C-states When PCIe* Links Are Disabled Performance Monitor Event For Outstanding Offcore Requests And Snoop Requests May Over Count Some Performance Monitor Event Counts May be Inaccurate During SMT Mode Timed MWAIT May Use Deadline of a Previous Execution The Upper 32 Bits of CR3 May be Incorrectly Used With 32-Bit Paging Performance Monitor Events HLE_RETIRED.ABORTED_MISC4 And RTM_RETIRED.ABORTED_MISC4 May Over Count A PCIe* LTR Update Message May Cause The Processor to Hang GETSEC Does Not Report Support...

Errata (Sheet 4 of 5) Steppings Number AVX Gather Instructions Page Faults May Report an Incorrect Faulting Address Intel® TSX Instructions May Cause Unpredictable System behavior Event Injection by VM Entry May Use an Incorrect B Flag for SS LPDDR3 ZQ Calibration Following Deep Package C-state Exit May Lead to Unpredictable System Behavior A Fault in SMM May Result in Unpredictable System Behavior Processor Frequency is Unexpectedly Limited Below Nominal P1 When cTDP Down is Enabled PMI May be Signaled More Than Once For Performance Monitor Counter Overflow Execution of FXSAVE or FXRSTOR...

Errata (Sheet 5 of 5) Steppings Number x87 FPU DP May be Incorrect After Instructions That Save FP State to Memory Processor May Hang During Package C7 Exit Certain Processors May Experience Transient LLC ECC Errors Intel® TSX Instructions May Cause Unpredictable System behavior Spurious LLC Machine Check May Occur Page Fault May Report Incorrect Fault Information CATERR# Pin Assertion is Not Cleared on a Warm Reset Uncorrectable Machine Check Error During Core C6 Entry May Not be Signaled The SAMPLE/PRELOAD JTAG Command Does Not Sample The Display Transmit Signals Performance Monitor Event...