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Mobile 4th Gen Intel® Core? Processor Family: Specification Update

Mobile 4th Gen Intel® Core? Processor Family: Specification Update

Product catalog summary

Overview: This document provides a specification update for the 4th Generation Intel® Core™ Processor Family, Mobile Intel® Pentium® Processor Family, and Mobile Intel® Celeron® Processor Family. It includes errata, specification changes, and clarifications aimed at hardware system manufacturers and software developers.

Legal and Usage Terms: The document emphasizes that it does not grant intellectual property rights and disclaims liability for use in mission-critical applications. Users must indemnify Intel against claims arising from such use.

Revision History: Since its initial release in June 2013, the document has undergone multiple revisions, focusing on errata additions and processor identification information.

Errata: Numerous errata affecting processor behavior are listed, such as incorrect address reporting and memory-ordering violations. These are categorized by stepping and status, indicating whether they are fixed or remain unaddressed.

Specification Changes and Clarifications: Changes to published specifications are documented, with clarifications provided for complex design situations. These updates will be incorporated into future releases of the specifications.

Documentation Changes: Corrections for typos, errors, or omissions in current specifications are included, which will be updated in future documentation releases.

Summary Tables of Changes: Tables summarize errata, specification changes, and clarifications, indicating their applicability to different processor steppings and their current status.

Processor Specifications: Detailed specifications for the 4th Generation Intel® Core™ Processor family are provided, focusing on Mobile M-Processor, H-Processor, U-Processor, and Y-Processor lines. Key parameters include S-Spec Number, Processor Number, Stepping, Cache Size, Functional Cores, Integrated Graphics Cores, Max Turbo Frequency, Memory Frequency, Core Frequency, and Thermal Design Power (TDP).

Errata Details: The document lists several errata affecting the processors, such as incorrect address reporting during exceptions, EFLAGS discrepancies, and memory-ordering violations. Each erratum includes implications and potential workarounds, although some issues have no identified workarounds.

Recommendations: For each erratum, implications and potential workarounds are provided. The status of each erratum is linked to specific processor steppings, as detailed in the Summary Table of Changes.

Technical Document Summary:

1. PCIe Link and Error Handling: Erratum involves the root port not acknowledging TLP requests, causing replay by the PCIe link partner. No workaround identified.

2. Local APIC Timer Interrupts: Timer interrupts may be delivered unexpectedly when CCR is 0, affecting software relying on LVT and IRR bits.

3. PCIe Compliance State and Transmitter Equalization: Incorrect de-emphasis levels may be used during compliance state transitions.

4. PCIe Error Logging: Errors may be incorrectly logged during state transitions.

5. Graphics Aperture Access: Accessing memory space 0-640K through the graphics aperture may cause unpredictable behavior.

6. PCIe Link Speed Change: Root port may not initiate link speed change without software trigger.

7. x87 FPU Exceptions: Pending exceptions may be signaled earlier than expected.

8. Debugging and Breakpoints: DR6.B0-B3 may not report all breakpoints matched.

9. VEX.L Bit Handling: VEX.L bit is not ignored, causing unexpected #UDs.

10. Boundary Scan Testing: Processor may shut down if HIGHZ TAP command is run improperly.

11. Performance Monitoring: Certain events may undercount or produce incorrect results.

12. PCIe Atomic Transactions: Starvation may occur with concurrent atomic transactions.

13. AVX Gather Instructions: EPT violations may prevent forward progress of gather instructions.

14. Core Voltage Reporting: MSR_PERF_STATUS may report incorrect core voltage.

15. PCIe Compliance Patterns: Modified compliance patterns do not follow PCIe specification.

16. Processor Shutdown on Errors: Processor may shut down unexpectedly on a second uncorrectable error.

17. Performance Monitor UOPS_EXECUTED Event: Event may undercount when eight UOPs execute in one cycle.

18. Corrected Error Count Overflow: Overflow bit not updated after a UC error is logged.

19. Graphics Controller Behavior: Specific blitter instructions may cause unpredictable behavior.

20. MSR Visibility: PLATFORM_POWER_LIMIT MSR not visible.

Specifications and Issues: Various issues are detailed, such as unreliable ACTIVITY.L2_ PENDING during SMT Mode, incorrect usage of upper 32 bits of CR3 with 32-bit paging, and performance monitoring events over counting transactional aborts.

Recommendations: For issues with identified BIOS workarounds, ensure BIOS updates are applied to mitigate errata. For software-related issues, developers should implement recommended practices to avoid errata implications. Regularly consult the Summary Table of Changes for updates on affected steppings and potential new workarounds.

MRAM State-Save Area: Located below the 4GB address boundary.

TM1 Throttling Issue: A hang may occur when TM1 throttling via IA32_CLOCK_MODULATION MSR is set with specific duty cycle values.

DMA Remapping Faults: Faults in DMA remapping for Graphics VT-d may not report the type of faulted request correctly.

Deep Package C-State Exit: Exiting deep package C-states may result in system hangs due to undefined VR behavior.

AVX Gather Instructions: Page faults may report incorrect faulting addresses if TLB invalidation is not performed.

Intel TSX Instructions: May cause unpredictable system behavior under certain conditions.

VM Entry Event Injection: May use incorrect B flag for stack segment, leading to unpredictable behavior.

LPDDR3 ZQ Calibration: Exiting deep package C-states may lead to unpredictable behavior in systems using LPDDR3 dual or quad die packages.

SMM Faults: May result in unpredictable behavior due to incorrect SS register and CPL values.

Processor Frequency Limitation: When cTDP Down is enabled, processor frequency may be limited below nominal P1.

PMI Signaling: May be signaled more than once for performance monitor counter overflow.

FXSAVE/FXRSTOR with VEX Prefix: May produce a #NM exception instead of #UD.

RDRAND in Transactional Region: May cause system hang.

Turbo Boost Technology Reporting: Incorrectly reported as supported on certain processors.

Uncore Clock Frequency Changes: May cause audio/video glitches.

LLC-Related Machine Check: May occur during high activity periods.

Package C7 Entry with PSR Display: Processor may not enter package C7 as expected.

Video/Audio Distortion: May occur due to delayed memory read requests.

System Hang with Audio Enabled: May occur during package C3 state.

INVPCID Instruction: May not cause #UD in VMX non-root operation as expected.

PFAT Module Base Address: Non-compliance may cause unpredictable behavior.

LBR Source Address Reporting: May be incorrect for transactional aborts.

VT-d Address Translation Faults: May not be reported for display engine memory accesses.

L3 Cache Error Count: May be inaccurate after package C7 exit.

PCIe Device SVID Preservation: Not preserved across package C7 transitions.

Warm Reset Power Draw: GT may remain powered after warm reset, affecting power management.

Unused PCIe Lanes Power State: May remain powered after package C7 exit, increasing power consumption.

BMI1 and BMI2 Instruction Groups: Not available on Intel® Core™ i3-4100M, causing a #UD fault when executed.

HD Audio Device Playback: Audio playback may be interrupted if the processor enters a deep package C-state.

Virtual-APIC Page Accesses: Accessing the virtual-APIC page with 32-bit PAE paging may cause a system crash.

Processor Energy Policy: Energy efficiency control may not work as expected when certain conditions are met.

Graphics Engine Frequency: Processor may not reduce the graphics engine's frequency during power or thermal events.

PEBS Record: PEBS records may contain processor state for an unexpected instruction.

MSR_PP1_ENERGY_STATUS: Reports incorrect energy data.

x87 FPU DP: Incorrect value after instructions that save FP state to memory.

Package C7 Exit: Processor may hang during package C7 exit.

LLC ECC Errors: Transient LLC ECC errors may occur under certain conditions.

Intel® TSX Instructions: May cause unpredictable system behavior.

Spurious LLC Machine Check: May occur under stressful conditions.

Page Fault Information: May report incorrect fault information.

CATERR# Pin Assertion: Not cleared on a warm reset.

Machine Check Error During Core C6 Entry: May not be signaled.

JTAG Command: Does not sample Display Transmit signals.

Performance Monitor Event: May be incorrect for outstanding offcore requests and snoop requests.

PCIe Link Training: May incorrectly train to 8.0 GT/s.

PCIe Tx Voltage Reference: Cannot be changed.

VM Exit and IA32_EFER.NXE: May set IA32_EFER.NXE when it should not.

Re-enabling eDRAM: May log a machine check and hang.

Warm Reset and EDRAM Power Draw: EDRAM remains powered after a warm reset.

Errata Overview: Various errata are detailed, such as incorrect power management after a warm reset, loss of CHAP counter values, and execution of opcode bytes F3 0F BC as TZCNT even if not enumerated by CPUID.

Specification Changes and Clarifications: No new specification changes or clarifications are introduced in this update.

Documentation Changes: No new documentation changes are introduced in this update. Future changes will be incorporated into the appropriate processor documentation.

On-Demand Clock Modulation Feature Clarification: The clarification addresses how the on-demand clock modulation feature operates differently across processors, particularly with Hyper-Threading Technology.

Catalog excerpts

Mobile 4th Gen Intel® Core? Processor Family: Specification Update-1

Mobile 4th Generation Intel® Core™ Processor Family, Mobile Intel® Pentium® Processor Family, and Mobile Intel® Celeron® Processor Family Specification Update Supporting 4th Generation Intel® Core™ Processor based on Mobile MProcessor and H-Processor Lines Supporting 4th Generation Intel® Core™ Processor based on Mobile UProcessor and Y-Processor Lines June 2014 Revision 012

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Mobile 4th Gen Intel® Core? Processor Family: Specification Update-2

By using this document, in addition to any agreements you have with Intel, you accept the terms set forth below. You may not use or facilitate the use of this document in connection with any infringement or other legal analysis concerning Intel products described herein. You agree to grant Intel a non-exclusive, royalty-free license to any patent claim thereafter drafted which includes subject matter disclosed herein. INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED...

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Specification Update

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Specification Update

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Revision History Revision 001 Description Initial Release. No Updates. Revision number added to Revision History to maintain consistency with NDA Specification Update numbering. Errata — Added D-0 stepping to errata summary table — Added HSM60-106 Updated Identification Information No Updates. Revision number added to Revision History to maintain consistency with NDA Specification Update numbering. Errata — Moved previous HSM106 to HSM116 — Added HSM106-115 and HSM117–125 Processor Identification — Updated Table 3, Processor Identification by Register Contents — Updated Table 4, 4th Generation...

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Mobile 4th Gen Intel® Core? Processor Family: Specification Update-6

Preface This document is an update to the specifications contained in the Affected Documents table below. This document is a compilation of device and documentation errata, specification clarifications and changes. It is intended for hardware system manufacturers and software developers of applications, operating systems, or tools. Information types defined in Nomenclature are consolidated into the specification update and are no longer published in other documents. This document may also contain information that was not previously published. Affected Documents Document Title Generation Intel®...

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Mobile 4th Gen Intel® Core? Processor Family: Specification Update-7

Document Title 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes ACPI Specifications Document Number/ Location http://www.intel.com/ content/www/us/en/ processors/architectures-softwaredevelopermanuals.html Nomenclature Errata are design defects or errors. These may cause the processor behavior to deviate from published specifications. Hardware and software designed to be used with any given stepping must assume that all errata documented for that stepping are present on all devices. S-Spec Number is a five-digit code used to identify products. Products are differentiated...

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Mobile 4th Gen Intel® Core? Processor Family: Specification Update-8

Summary Tables of Changes The following tables indicate the errata, specification changes, specification clarifications, or documentation changes which apply to the processor. Intel may fix some of the errata in a future stepping of the component, and account for the other outstanding issues through documentation or specification changes as noted. These tables uses the following notations. Codes Used in Summary Tables Stepping X: Errata exists in the stepping indicated. Specification Change or Clarification that applies to this stepping. This erratum is fixed in listed stepping or specification...

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Mobile 4th Gen Intel® Core? Processor Family: Specification Update-9

Errata (Sheet 1 of 5) Steppings Number LBR, BTS, BTM May Report a Wrong Address when an Exception/ Interrupt Occurs in 64-bit Mode EFLAGS Discrepancy on Page Faults and on EPT-Induced VM Exits after a Translation Change MCi_Status Overflow Bit May Be Incorrectly Set on a Single Instance of a DTLB Error MONITOR or CLFLUSH on the Local XAPIC's Address Space Results in Hang An Uncorrectable Error Logged in IA32_CR_MC2_STATUS May also Result in a System Hang #GP on Segment Selector Descriptor that Straddles Canonical Boundary May Not Provide Correct Exception Error Code FREEZE_WHILE_SMM Does Not...

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Mobile 4th Gen Intel® Core? Processor Family: Specification Update-10

Errata (Sheet 2 of 5) Steppings Number Performance Monitor Counters May Produce Incorrect Results Performance Monitor UOPS_EXECUTED Event May Undercount MSR_PERF_STATUS May Report an Incorrect Core Voltage PCIe* Atomic Transactions From Two or More PCIe Controllers May Cause Starvation The Corrected Error Count Overflow Bit in IA32_ MC0_STATUS is Not Updated After a UC Error is Logged An AVX Gather Instruction That Causes an EPT Violation May Not Update Previous Elements LPDDR Memory May Report Incorrect Temperature PCIe* Host Bridge DID May Be Incorrect TSC May be Incorrect After a Deep C-State...

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Mobile 4th Gen Intel® Core? Processor Family: Specification Update-11

Errata (Sheet 3 of 5) Steppings Number Processor May Not Enter Package C6 or Deeper C-states When PCIe* Links Are Disabled Performance Monitor Event For Outstanding Offcore Requests And Snoop Requests May Over Count Some Performance Monitor Event Counts May be Inaccurate During SMT Mode Timed MWAIT May Use Deadline of a Previous Execution The Upper 32 Bits of CR3 May be Incorrectly Used With 32-Bit Paging Performance Monitor Events HLE_RETIRED.ABORTED_MISC4 And RTM_RETIRED.ABORTED_MISC4 May Over Count A PCIe* LTR Update Message May Cause The Processor to Hang GETSEC Does Not Report Support For...

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Mobile 4th Gen Intel® Core? Processor Family: Specification Update-12

Errata (Sheet 4 of 5) Steppings Number AVX Gather Instructions Page Faults May Report an Incorrect Faulting Address Intel® TSX Instructions May Cause Unpredictable System behavior Event Injection by VM Entry May Use an Incorrect B Flag for SS LPDDR3 ZQ Calibration Following Deep Package C-state Exit May Lead to Unpredictable System Behavior A Fault in SMM May Result in Unpredictable System Behavior Processor Frequency is Unexpectedly Limited Below Nominal P1 When cTDP Down is Enabled PMI May be Signaled More Than Once For Performance Monitor Counter Overflow Execution of FXSAVE or FXRSTOR With...

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Mobile 4th Gen Intel® Core? Processor Family: Specification Update-13

Errata (Sheet 5 of 5) Steppings Number x87 FPU DP May be Incorrect After Instructions That Save FP State to Memory Processor May Hang During Package C7 Exit Certain Processors May Experience Transient LLC ECC Errors Intel® TSX Instructions May Cause Unpredictable System behavior Spurious LLC Machine Check May Occur Page Fault May Report Incorrect Fault Information CATERR# Pin Assertion is Not Cleared on a Warm Reset Uncorrectable Machine Check Error During Core C6 Entry May Not be Signaled The SAMPLE/PRELOAD JTAG Command Does Not Sample The Display Transmit Signals Performance Monitor Event For...

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