Mobile 3rd Generation Intel® Core? Processor Family Specification Update
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Mobile 3rd Generation Intel® Core™ Processor Family Specification Update June 2014 Revision 018

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Specification Update

Specification Update

Revision History Revision Initial Release. Added Errata BU69–BU85 Updated Processor Identification Table Added L-1 stepping to Component Identification using Programming Added L-1 stepping to errata summary table Updated Processor Identification Table Added Mobile 3rd Generation Intel® Core™ i7-3940XM, i7-3840QM, i7-3740QM processors Documentation Change Added Errata BU105, BU106, BU107, BU108 Made changes to Erratum BU101 Removed repeating erratum BU108 Revised erratum BU101 to show only supported performance counters August 2013 September 2013 January 2014 March 2014 June 2014...

Preface This document is an update to the specifications contained in the Affected Documents table below. This document is a compilation of device and documentation errata, specification clarifications and changes. It is intended for hardware system manufacturers and software developers of applications, operating systems, or tools. Information types defined in Nomenclature are consolidated into the specification update and are no longer published in other documents. This document may also contain information that was not previously published. Affected Documents Document Title Mobile 3rd...

Nomenclature Errata are design defects or errors. These may cause the processor behavior to deviate from published specifications. Hardware and software designed to be used with any given stepping must assume that all errata documented for that stepping are present on all devices. S-Spec Number is a five-digit code used to identify products. Products are differentiated by their unique characteristics such as, core speed, L2 cache size, package type, etc. as described in the processor identification information table. Read all notes associated with each S-Spec number. Specification Changes...

Summary Tables of Changes The following tables indicate the errata, specification changes, specification clarifications, or documentation changes which apply to the processor. Intel may fix some of the errata in a future stepping of the component, and account for the other outstanding issues through documentation or specification changes as noted. These tables uses the following notations: Codes Used in Summary Tables Stepping X: Errata exists in the stepping indicated. Specification Change or Clarification that applies to this stepping. This erratum is fixed in listed stepping or...

Errata (Sheet 2 of 5) Steppings Number General Protection Fault (#GP) for Instructions Greater than 15 Bytes May be Preempted LBR, BTS, BTM May Report a Wrong Address when an Exception/Interrupt Occurs in 64-bit Mode Incorrect Address Computed For Last Byte of FXSAVE/FXRSTOR or XSAVE/XRSTOR Image Leads to Partial Memory Update Values for LBR/BTS/BTM Will be Incorrect after an Exit from SMM EFLAGS Discrepancy on Page Faults and on EPT-Induced VM Exits after a Translation Change B0-B3 Bits in DR6 For Non-Enabled Breakpoints May be Incorrectly Set MCi_Status Overflow Bit May Be Incorrectly Set...

Errata (Sheet 3 of 5) Steppings Number Processor May Fail to Acknowledge a TLP Request An Unexpected PMI May Occur After Writing a Large Value to IA32_FIXED_CTR2 A Write to the IA32_FIXED_CTR1 MSR May Result in Incorrect Value in Certain Conditions PCIe* LTR Incorrectly Reported as Being Supported PerfMon Overflow Status Can Not be Cleared After Certain Conditions Have Occurred #GP May be Signaled When Invalid VEX Prefix Precedes Conditional Branch Instructions Interrupt From Local APIC Timer May Not Be Detectable While Being Delivered PCI Express* Differential Peak-Peak Tx Voltage Swing...

Errata (Sheet 4 of 5) Steppings Number PCIe* Root-port Initiated Compliance State Transmitter Equalization Settings May be Incorrect PCIe* Controller May Incorrectly Log Errors on Transition to RxL0s Reception of Certain Malformed Transactions May Cause PCIe* Port to Hang Rather Than Reporting an Error PCIe* Link Width May Degrade After a Warm Reset MSR_PKG_Cx_RESIDENCY MSRs May Not be Accurate Execution of Package C7 May Result in a Hang PCIe* Link May Not Enter Loopback.Active When Directed Execution of VAESIMC or VAESKEYGENASSIST With An Illegal Value for VEX.vvvv May Produce a #NM...

Errata (Sheet 5 of 5) Steppings Number Instruction Fetches Page-Table Walks May be Made Speculatively to Uncacheable Memory The Processor May Not Properly Execute Code Modified Using A Floating-Point Store Execution of GETSEC[SEXIT] May Cause a Debug Exception to be Lost VM Exits Due to GETSEC May Save an Incorrect Value for “Blocking by STI” in the Context of Probe-Mode Redirection Specific Graphics Blitter Instructions May Result in Unpredictable Graphics Controller Behavior IA32_MC5_CTL2 is Not Cleared by a Warm Reset CPUID Instruction May Not Report the Processor Number in the Brand...

Specification Update

Identification Information Component Identification using Programming Interface The processor stepping can be identified by the following register contents: Reserved Notes: 1. The Extended Family, bits [27:20] are used in conjunction with the Family Code, specified in bits [11:8], to indicate whether the processor belongs to the Intel386, Intel486, Pentium, Pentium Pro, Pentium 4, or Intel® Core™ processor family. 2. The Extended Model, bits [19:16] in conjunction with the Model Number, specified in bits [7:4], are used to identify the model of the processor within the processor’s family....