Intel® Xeon® Processor E3-1200 v5
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Intel® Xeon® Processor E3-1200 v5 Product Family Datasheet - Volume 1 of 2 October 2015

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Intel® Xeon® Processor E3-1200 v5 Product Family Datasheet, Volume 1 of 2

Intel® Xeon® Processor E3-1200 v5 Product Family Datasheet, Volume 1 of 2

Intel® Xeon® Processor E3-1200 v5 Product Family Datasheet, Volume 1 of 2

Intel® Xeon® Processor E3-1200 v5 Product Family Datasheet, Volume 1 of 2

Intel® Xeon® Processor E3-1200 v5 Product Family Datasheet, Volume 1 of 2

Intel® Xeon® Processor E3-1200 v5 Product Family Datasheet, Volume 1 of 2

Revision History Revision Number 001 Initial release Revision Date October 2015 Intel® Xeon® Processor E3-1200 v5 Product Family Datasheet, Volume 1 of 2

Introduction The, Intel® Xeon® Processor E3-1200 v5 product family are a 64-bit, multi-core processor built on 14-nanometer process technology. The Intel® Xeon® Processor E3-1200 v5 line processors are offered in a 2-Chip Platform and are connected to a discrete Intel® C230 Series Chipset Family Platform Controller Hub on the motherboard. See the following figure. Some of the processor SKUs are offered with On-Package Cache. This document covers all processor workstation (WS) and server (SRV) segments based on the new Intel® Xeon® Processor E3-1200 v5 processor architecture. Not all...

Supported Technologies • Intel® Virtualization Technology (Intel® VT) • Intel® Active Management Technology 11.0 (Intel® AMT 11.0) • Intel® Trusted Execution Technology (Intel® TXT) • Intel® Streaming SIMD Extensions 4.2 (Intel® SSE4.2) • Intel® Hyper-Threading Technology (Intel® HT Technology) • Intel® 64 Architecture • Execute Disable Bit • Intel® Turbo Boost Technology 2.0 • Intel® Advanced Vector Extensions 2 (Intel® AVX2) • Intel® Advanced Encryption Standard New Instructions (Intel® AES-NI) • PCLMULQDQ (Perform Carry-Less Multiplication Quad word) Instruction • Intel® Secure Key •...

• DRAM Power Management and Initialization • Initialization Role of CKE • Conditional Self-Refresh • Dynamic Power Down • DRAM I/O Power Management • DDR Electrical Power Gating (EPG) • Power training Refer to Section 4.3 for more information. Processor Graphics Power Management Memory Power Savings Technologies • Intel® Rapid Memory Power Management (Intel® RMPM) • Intel® Smart 2D Display Technology (Intel® S2DDT) Display Power Savings Technologies • Intel® (Seamless & Static) Display Refresh Rate Switching (DRRS) with eDP* port • Intel® Automatic Display Brightness • Smooth Brightness •...

• Intel® Turbo Boost Technology 2.0 Power Control Refer to Chapter 5, “Thermal Management” for more information. Package Support The processor is available in the following package: • A 37.5 mm x 37.5 mm LGA package (LGA1151) Processor Testability An XDP on-board connector is a must to enable the processor full debug capabilities. For the processor SKUs, a merged XDP connector is highly recommended to enable lower C-state debug. When separate XDP connectors will be used at C8–C10 states, the processor will need to be waked up using the PCH. Merged XDP Connector for Processor and PCH The...

Terminology (Sheet 2 of 3) Term Fourth-Generation Double Data Rate SDRAM Memory Technology RS - Reduced Standby Power Decision Feedback Equalizer Direct Memory Access Direct Media Interface Digital Thermal Sensor Error Correction Code - used to fix DDR transactions errors embedded DisplayPort* Execution Unit in the Processor Graphics Graphics in System Agent High-bandwidth Digital Content Protection High Definition Multimedia Interface Integrated Memory Controller 64-bit memory extensions to the IA-32 architecture Intel® DPST Intel Display Power Saving Technology Intel Platform Trust...

Terminology (Sheet 3 of 3) Term Platform Controller Hub. The chipset with centralized platform capabilities including the main I/O interfaces along with display connectivity, audio features, power management, manageability, security, and storage features. The PCH may also be referred as “chipset”. Platform Environment Control Interface Power Limit 1, Power Limit 2, Power Limit 3 The 64-bit multi-core component (package) Processor Core The term “processor core” refers to Si die itself, which can contain multiple execution cores. Each execution core has an instruction cache, data cache, and...

Related Documents Related Documents Document Document Number / Location Intel® Xeon® Processor E3-1200 v5 Product Family Datasheet, Volume 2 of 2 6th Generation Intel® Core Processor Family Specification Update 6th Generation Intel® Processor Platform I/O Datasheet, Volume 1 of 2 6th Generation Intel® Processor Platform I/O Datasheet, Volume 2 of 2 6th Generation Intel® Processor Platform I/O Specification Update Advanced Configuration and Power Interface 3.0 High Definition Multimedia Interface specification revision 1.4 embedded DisplayPort* Specification revision 1.4 DisplayPort*...

System Memory Interface • Two channels of DDR3L/-RS and DDR4/-RS memory with a maximum of two DIMMs per channel. DDR technologies, number of DIMMs per channel, number of ranks per channel are SKU dependent. • UDIMM and Memory Down support (based on SKU) • Single-channel and dual-channel memory organization modes • Data burst length of eight for all memory organization modes • DDR3L/-RS I/O Voltage of 1.35V - based on processor line • DDR4/-RS I/O Voltage of 1.2V • 64-bit wide channels • ECC UDIMM DDR4/DDR3L/-RS support • Theoretical maximum memory bandwidth of: — 21.3 GB/s in dual-channel...