Intel® Xeon® Processor 5000 Series Datasheet
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Document Number: 313079-001 Dual-Core Intel® Xeon® Processor 5000 Series Datasheet May 2006

2 Dual-Core Intel® Xeon® Processor 5000 Series Datasheet INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY...

Dual-Core Intel® Xeon® Processor 5000 Series Datasheet 7 Revision History Revision Description Date 001 Initial release May 2006

8 Dual-Core Intel® Xeon® Processor 5000 Series Datasheet Features .. Dual-Core processor .. Available at 3.73 GHz processor speed .. Includes 16-KB Level 1 data cache per core (2 x 16-KB) .. Includes 12-KB Level 1 trace cache per core (2 x 12-KB) .. 2-MB Advanced Transfer Cache per core (2 x 2-MB, On-die, full speed Level 2 (L2) Cache) with 8- way associativity and Error Correcting Code (ECC) .. 667/1066 MHz front side bus .. 65 nm process technology .. Dual processing (DP) server support .. Intel® NetBurst® microarchitecture .. Hyper-Threading Technology allowing up to 8 threads per...

Dual-Core Intel® Xeon® Processor 5000 Series Datasheet 9 Introduction 1 Introduction The Dual-Core Intel® Xeon® Processor 5000 series are Intel dual core products for dual processor (DP) servers and workstations. The Dual-Core Intel Xeon Processor 5000 series are 64-bit server/workstation processors utilizing two physical Intel NetBurst® microarchitecture cores in one package. The Dual-Core Intel Xeon Processor 5000 series include enhancements to the Intel NetBurst microarchitecture while maintaining the tradition of compatibility with IA-32 software. Some key features include Hyper...

Introduction 10 Dual-Core Intel® Xeon® Processor 5000 Series Datasheet and can thus help improve the overall security of the system. For further information on Execute Disable Bit functionality see http://www.intel.com/cd/ids/developer/asmo-na/ eng/149308.htm. The Dual-Core Intel Xeon Processor 5000 series support Intel® Virtualization Technology, virtualization within the processor. Intel Virtualization Technology is a set of hardware enhancements that can improve virtualization solutions. Intel Virtualization Technology is used in conjunction with Virtual Machine Monitor software enabling...

Dual-Core Intel® Xeon® Processor 5000 Series Datasheet 11 Introduction 1.1 Terminology A ‘#’ symbol after a signal name refers to an active low signal, indicating a signal is in the asserted state when driven to a low level. For example, when RESET# is low, a reset has been requested. Conversely, when NMI is high, a nonmaskable interrupt has occurred. In the case of signals where the name does not imply an active state but describes part of a binary sequence (such as address or data), the ‘#’ symbol implies that the signal is inverted. For example, D[3:0] = ‘HLHL’ refers to a hex ‘A’, and...

Introduction 12 Dual-Core Intel® Xeon® Processor 5000 Series Datasheet • Thermal Design Power – Processor thermal solutions should be designed to meet this target. It is the highest expected sustainable power while running known power intensive real applications. TDP is not the maximum power that the processor can dissipate. • LGA771 socket – The Dual-Core Intel Xeon Processor 5000 series interfaces to the baseboard through this surface mount, 771 Land socket. See the LGA771 Socket Design Guidelines for details regarding this socket. • Processor – A single package that contains one or more...

Dual-Core Intel® Xeon® Processor 5000 Series Datasheet 13 Introduction Notes: Contact your Intel representative for the latest revision of those documents. § Dual-Core Intel® Xeon® Processor 5000 Series Specifications Update 313065 EPS12V Power Supply Design Guide: A Server system Infrastructure (SSI) Specification for Entry Chassis Power Supplies http:// www.ssiforum.org Entry-Level Electronics-Bay Specifications: A Server System Infrastructure (SSI) Specification for Entry Pedestal Servers and Workstations http:// www.ssiforum.org Dual-Core Intel® Xeon® Processor 5000 Series...

Introduction 14 Dual-Core Intel® Xeon® Processor 5000 Series Datasheet

Dual-Core Intel® Xeon® Processor 5000 Series Datasheet 15 Electrical Specifications 2 Electrical Specifications 2.1 Front Side Bus and GTLREF Most Dual-Core Intel Xeon Processor 5000 series FSB signals use Assisted Gunning Transceiver Logic (AGTL+) signaling technology. This technology provides improved noise margins and reduced ringing through low voltage swings and controlled edge rates. AGTL+ buffers are open-drain and require pull-up resistors to provide the high logic level and termination. AGTL+ output buffers differ from GTL+ buffers with the addition of an active PMOS pull-up...

Electrical Specifications 16 Dual-Core Intel® Xeon® Processor 5000 Series Datasheet 2.3 Decoupling Guidelines Due to its large number of transistors and high internal clock speeds, the Dual-Core Intel Xeon Processor 5000 series are capable of generating large average current swings between low and full power states. This may cause voltages on power planes to sag below their minimum values if bulk decoupling is not adequate. Larger bulk storage (CBULK), such as electrolytic capacitors, supply current during longer lasting changes in current demand by the component, such as coming out of an...

Dual-Core Intel® Xeon® Processor 5000 Series Datasheet 17 Electrical Specifications The processor core frequency is configured during reset by using values stored internally during manufacturing. The stored value sets the highest bus fraction at which the particular processor can operate. If lower speeds are desired, the appropriate ratio can be configured via the IA32_FLEX_BRVID_SEL MSR. For details of operation at core frequencies lower than the maximum rated processor speed, refer to the IA-32 Intel® Architecture Software Developer’s Manual, Volume 3A &3B. Clock multiplying within the...