Intel® Quark™ SoC X1000 Series
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Intel® Quark™ SoC X1000 Datasheet August 2015

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August 2015 Document Number: 329676-005US Intel® Quark™ SoC X1000 Datasheet 3

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Tables Intel® Quark™ SoC X1000 Datasheet 32 August 2015 Document Number: 329676-005US

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Intel® Quark™ SoC X1000—Revision History Revision History Updated Section 18.3.1, “DMA Mode Operation” on page 665 Updated Section 18.3.4, “Autoflow Control” on page 667 Updated Section 9.2.3, “AC Power Applied: G3 to S4/S5 State Transition” on page 115 Updated Section 9.2.4, “Using PWR_BTN_B: Transition from S4/S5 to S0” on page 116 Updated Updated Updated Updated Updated Updated Updated Updated Table 23, “Hardware Straps” on page 57 subsection numbering under Section 12.6.2, “SPI DMA Block” on page 140 Table 27, “Power Supply Rail Ranges” on page 70 Table 28, “Maximum Supply Current: ICC...

About This Manual This document is intended for Original Equipment Manufacturers and BIOS vendors creating products based on the Intel® Quark™ SoC X1000 application processor. Throughout this document, SoC is used as a general term and refers to all Intel® Quark™ SoC X1000 SKUs, unless specifically noted otherwise. This manual assumes a working knowledge of the vocabulary and principles of interfaces and architectures such as PCI Express*, USB, SDIO/MMC, and ACPI. Although some details of these features are described within this manual, refer to the individual industry specifications listed...

To enable secure applications, the SoC secure SKUs feature an on-die Boot ROM that is used to establish a hardware Root of Trust (RoT). The immutable code located within the Boot ROM is used to initiate an iterative firmware authentication process ensuring only trusted code is executed when taking the platform out of reset. To facilitate low-cost platforms with sensitive Bill of Material (BOM) requirements, all SoC clocks can be generated from a single crystal oscillator while all the required SoC voltage levels can be derived from a single commercial off-the-shelf (COTS) voltage regulator....

• 32-bit address bus, 32-bit data bus • 16 Kbyte shared instruction and data L1 cache. System Memory Controller Features • Single channel DDR3 memory controller with ECC support • 16-bit data bus • Supports up to two ranks total • Supports DDR3 with 800 MT/s data rates • x8 DRAM device data width • 1 Gbit, 2 Gbit, and 4 Gbit DRAM device densities • Total memory size from 128 Mbyte to 2 Gbyte • Supports different physical mappings of bank addresses to optimize performance • Out-of-order request processing to increase performance • Aggressive power management to reduce power consumption •...