*mydirectindustry

Catalogs
Intel
Intel® Core? i7 Processor for LGA2011 Socket: Datasheet, Vol. 2

Intel® Core? i7 Processor for LGA2011 Socket: Datasheet, Vol. 2

Product catalog summary

Introduction
This document is the second volume of the datasheet for the Intel® Core™ i7 Processor Family designed for the LGA2011 socket. It supports the Intel® Core™ i7-4960X Extreme Edition and other i7-49xx and i7-48xx series processors. The document includes legal disclaimers, emphasizing that Intel provides no warranty for the use of its products in mission-critical applications and that specifications may change without notice.

Registers Overview and Configuration Process
This section details the platform configuration structure, including processor IIO and uncore devices. It explains configuration register rules, such as CSR access, PCI bus numbers, and device mapping. Memory-mapped I/O registers and register terminology are also covered.

Integrated Memory Controller (IMC) Configuration Registers
The document provides an extensive list of configuration registers for the Integrated Memory Controller. It includes detailed descriptions of various registers such as pxpcap, mcmtr, and tadwayness, among others. Each register's function and configuration are explained, providing essential information for system designers.

Key Considerations
- Intel's legal disclaimers highlight the absence of warranties for specific uses and potential changes in specifications.
- The document emphasizes the importance of consulting Intel's resources for the latest specifications and errata.
- Overclocking and virtualization technologies are discussed, with warnings about potential impacts on system stability and performance.

Conclusion
This datasheet is a technical resource for developers and engineers working with Intel's LGA2011 socket processors. It provides detailed information on configuration registers and system requirements, essential for optimizing processor performance and ensuring compatibility.

Document Terminology
The document includes a glossary of terms such as DDR3, DMA, DMI2, and Intel® Turbo Boost Technology, among others. These terms are essential for understanding the processor's functionalities and features.

Related Documents
A list of related documents is provided for further reference, including datasheets, thermal mechanical specifications, and design guides.

Processor IIO Devices
The processor IIO includes devices such as the DMI2 Root Port, PCI Express* Root Ports, and the Integrated I/O Core. Each device contains specific registers for configuration and management.

Processor Uncore Devices
These devices are mapped on the PCI bus assigned to the processor socket and include the Processor Power Control Unit, Processor Interrupt Event Handling, Processor Core Broadcast, Processor Home Agent, and Integrated Memory Controllers. Each device has specific functions and registers for configuration and performance monitoring.

Processor Uncore Devices Map
This section outlines the mapping of various processor uncore devices, including the Integrated Memory Controller, Processor Core Broadcast, CPU Interrupt Handling, CPU Home Agents, Performance Monitoring, Power Control Unit, and DDRIO. Each device is associated with specific bus numbers and functions, which are crucial for configuration and performance monitoring.

Configuration Register Rules
The processor supports different types of configuration registers, including PCI Configuration Registers, Machine Specific Registers, and Memory-Mapped I/O Registers. The document explains how these registers are accessed and the rules governing their use, such as the use of little-endian ordering for multi-byte numeric fields.

Device Mapping and Bus Numbers
Each processor component is identified by a PCI bus address, consisting of Bus Number, Device Number, and Function Number. The document explains how bus numbers are derived and the significance of the CPUBUSNO register in determining the bus number for PCIe devices.

Unimplemented Devices and Device Hiding
The document discusses the handling of unimplemented devices and functions, noting that configuration reads to these will return all ones, emulating a master abort response. It also describes the mechanism for hiding devices from host configuration software using the DEVHIDE register.

Memory-Mapped I/O Registers
This section explains the role of memory-mapped I/O registers in driver programming and how they are accessed through processor reads and writes. It highlights the integration of chipset functionality that includes these registers.

Register Terminology and Attributes
The document provides a comprehensive list of register attributes, such as Read Only, Read/Write, and Write 1 to Set, among others. It explains the significance of each attribute and how they affect register behavior.

Notational Conventions
The document outlines the conventions used for representing hexadecimal, binary, and decimal numbers, ensuring clarity in the documentation of register addresses and values.

Integrated Memory Controller (IMC) Configuration Registers
This section provides a detailed address map for the IMC Device 15 Function 0, listing various registers, their offsets, sizes, and descriptions. It includes information on PCI Express Capability and other configuration details.

Overview: This document provides detailed technical specifications and configuration registers for the Integrated Memory Controller (IMC) with a focus on TSOD sensors, SMBus configurations, and DIMM temperature management.

1. TSOD Sensor Configuration:

Bits 7 and 3 must be programmed to zero as upper and lower channel slot #3 are not supported.
Bits 6-4 and 2-0 indicate the presence of TSOD sensors in various slots of upper and lower channels.

2. SMBus Configuration:

SMB_TSOD_POLL_RATE_CNTR: This counter resets or loads a new value when decremented to zero, affecting the TSOD poll rate.
SMBus Clock Period Configuration: Includes settings for clock period and time-out configurations, with specific values for different time-out durations.

3. DIMM Memory Technology:

Configuration registers for DIMM memory technology include settings for rank disable control, DIMM population, rank count, DDR3 width, and density.
Specific bits control the disabling of ranks and the configuration of DDR3 width and density.

4. Temperature Management:

chn_temp_cfg: Controls temperature tracking and thermal bandwidth throttling.
dimm_temp_oem: Sets threshold values for system interrupts based on temperature changes.
dimm_temp_th: Configures thresholds for critical, high, and mid-level temperature alerts.
dimm_temp_ev_ofst: Manages temperature averaging and MEMHOT event assertions based on temperature thresholds.

5. Additional Configuration Registers:

Registers for device functions and capabilities, including PCI Express compliance and capability pointers.
Specific offsets and default values are provided for each configuration setting.

Event Assertions and Interrupts:
1. Events are asserted when temperature thresholds (TEMPHI, TEMPMID, TEMPLO, TEMPOEMLO, TEMPOEMHI) are crossed. Each event triggers a configurable interrupt, either MEMHOT# or both SMI and MEMHOT#, as defined in bit 30 of CHN_TEMP_CFG.

DIMM Temperature Management:
- The DIMM temperature is used for thermal throttling and can be manipulated for testing when unlocked. The temperature range is 0 to 127°C, with a default of 85°C to prevent refresh issues during certain operations.

Power Throttling:
- Power throttling is controlled by the THRT_PWR_EN bit, allowing a maximum number of transactions during a 1 µs timeframe. This can be dynamically updated by PCODE.

Timing Constraints:
- Various timing parameters are defined for DDR3 operations, including T_RAS, T_CWL, T_CL, T_RP, T_RCD, and others. These parameters ensure proper operation and prevent timing violations.

Refresh and Calibration Parameters:
- Refresh timing parameters like T_RFC and T_REFI are specified for different DDR3 speeds. ZQ calibration timing is also defined to ensure proper operation.

Shadow Registers:
- MR2 and MR0 shadow registers are used for storing configuration settings related to address swizzling and mode register settings.

Recommendations:
- Set panic and high watermark levels for refresh priorities to optimize refresh periods. Ensure timing parameters meet DDRIO requirements to avoid violations.

Integrated Memory Controller (IMC) Configuration Registers Overview

1. MR0 Shadow Register: This section describes the MR0_SHADOW register, which is programmed by the BIOS for all DIMMs in a channel. It controls the fast and slow exit PPD through MRS to MR0. The register field defines address bits A[11:0], while A15:A13 are always zero.

2. Page Closing Policy: The document outlines a page closing policy aimed at balancing Premature Page Closes (PPCs) and Overdue Page Closes (OPCs) to minimize costly Page Misses. The policy tracks PPCs and OPCs over a configurable window and adjusts page closing times based on thresholds.

3. RPQ Age Counter: This counter tracks non-isoch transactions issued from HA, increasing with each CAS command. When the counter matches a configured value, the transaction is aged to the next priority level.

4. Page Mode Configuration: The ADAPT_PG_CLSE register works with MCMTR.CLOSEPG to enable Closed Page Mode, Open Page Mode, or Adaptive Open Mode. Illegal configurations are noted, and the idle timer settings are described.

5. Timing Control: Various timing parameters are detailed, including T_STAB for stabilizing time, T_MRD for command delay, and T_CKEV and T_CKOFF for input buffer timings. Recommended settings for different frequencies are provided.

6. Corrected Error Counters: The document describes registers for tracking corrected error counts per rank, including overflow handling and threshold settings. It emphasizes the importance of BIOS intervention for clearing overflow states.

7. Leaky Bucket Counter: This section explains the secondary leaky bucket counter logic, which helps manage correctable error counts by generating LEAK pulses based on predefined limits.

8. Device Tagging: The SDDC usage model is discussed, where hardware generates interrupts when error counts exceed thresholds. Device tagging enables substitution of failing devices with parity, with specific guidelines for independent and lock-step channel configurations.

Overview: The document provides detailed technical specifications and configurations for various components within a system, focusing on memory controllers, processor utility boxes, and power controller units. It includes information on enabling and managing features like DDDC (Double Device Data Correction), SDDC (Single Device Data Correction), and various registers associated with these components.

1. DDDC and SDDC Configuration:

DDDC can be enabled on supported systems through BIOS settings, allowing for faster sparing with SDDC substitution.
The Fail Device ID captures the ID of a failed device upon successful correction, with a valid range of 0-35 for x4 devices.

2. Integrated Memory Controller (IMC) Configuration:

Details on various registers and their offsets are provided, including device IDs, command statuses, and configuration registers.

3. Processor Utility Box (UBOX) Registers:

The UBOX handles non-mainstream flows such as register accesses and interrupt flows.
Registers include CPUNODEID, IntControl, GIDNIDMAP, CoreCount, and UBOXErrSts, each with specific configurations and functions.

4. Power Controller Unit (PCU) Register:

Registers report thermal status, accumulated bandwidth, and power settings for memory channels.
PACKAGE_POWER_SKU defines power and timing parameters, while PACKAGE_ENERGY_STATUS tracks energy consumption.

5. Key Parameters and Settings:

Temperature and power units are defined for various registers, impacting how power and thermal data are calculated and reported.
P-State limits allow software to control maximum frequency during runtime.

Conclusion: The document provides comprehensive details on configuring and managing system components, emphasizing error correction, power management, and system performance optimization.

Thermal Monitor Reference Temperature (REF_TEMP): This section describes the maximum junction temperature, also known as the throttle temperature, TCC activation temperature, or prochot temperature. It is the temperature at which the Thermal Monitor is activated. The firmware updates this register with a value calculated as 125 minus FUSETJMAXOFFSET.

Fan Temperature Target Offset (FAN_TEMP_TARGET_OFST): Also known as T-Control, this indicates the relative offset from the Thermal Monitor Trip Temperature at which fans should be engaged. It is part of the configuration registers with specific bus, device, and function identifiers.

Configuration Registers Overview: The document outlines two distinct CSR register spaces supported by the IIO Module: traditional PCI-defined configuration registers and MMIO space for Intel VT-d, RCRB, and I/OxAPIC runtime registers. It also discusses the handling of unimplemented devices/functions and registers, advising against software attempts to access these.

MMIO BARs in IIO: The document provides a table listing BDF:BAR# for various MMIO BARs in the IIO module, necessary for accessing MMIO registers over the message channel.

PCI vs. PCIe Device/Function: It differentiates between PCI and PCIe devices/functions, noting that PCI devices do not have a PCIe capability register set and do not decode offsets 100h and beyond.

Device and Function Details: The document details the function numbers of active root ports based on port bifurcation for various devices and functions, providing tables for ports 1, 2, and 3.

Integrated I/O Register Address Map: A comprehensive address map is provided, detailing register names, offsets, sizes, and applicable devices/functions.

PCI Command and Status Registers: The document explains various bits within the PCI command and status registers, including interrupt disable, SERR enable, and parity error response, among others. It provides detailed descriptions of each bit's function and default settings.

Overview: This document provides detailed information on the Integrated I/O (IIO) Configuration Registers for PCI Express* interfaces. It outlines various error conditions, register settings, and configuration parameters essential for managing PCI Express* ports.

Error Conditions: The document describes specific conditions that trigger error bits in the PCI Express* interface. For instance, bit 13 is set when a device receives a completion with an Unsupported Request or master abort status. Bit 12 is set for completer abort conditions on the primary interface.

Register Descriptions: Each register is detailed with its bit attributes, default values, and descriptions. Key registers include:

Secondary Status Register: Contains bits for detecting parity errors, system errors, and master abort statuses.
Primary Bus Number Register: Used to program the bus number on the primary side of the bridge.
Memory Base and Limit Registers: Define memory address ranges for PCI Express* ports, ensuring proper forwarding of memory transactions.
Prefetchable Memory Base and Limit Registers: Manage 64-bit prefetchable memory address ranges for efficient data handling.

Configuration Parameters: The document specifies configuration parameters such as bus numbers, memory base addresses, and I/O address limits. These parameters are crucial for setting up and maintaining PCI Express* interfaces.

Key Notes: Several notes highlight important considerations, such as the need to clear specific bits before programming registers and the alignment requirements for memory and I/O address ranges.

Conclusion: This technical document serves as a comprehensive guide for configuring and managing PCI Express* interfaces, detailing error handling, register settings, and configuration protocols.

Memory Address Alignment and Prefetchable Memory:
The memory address range is aligned to a 1MB boundary, with the top of the range being one less than a 1MB boundary. The bottom 4 bits of the Prefetchable Memory Base and Limit registers indicate if the bridge supports 64-bit addresses. A value of 0h means only 32-bit addresses are supported, while 1h indicates 64-bit support, utilizing additional registers for the upper 32 bits. Setting the memory limit below the base disables the 64-bit range.

Configuration Registers:

Capability Pointer (capptr): Points to the first capability structure, specifically the PCIe capability.
Interrupt Line and Pin Registers (intl, intpin): These registers are not applicable for the devices mentioned.
Bridge Control Register (bctrl): Controls various functions such as hot reset, VGA I/O decoding, and error message forwarding.
Subsystem Capability Identity (scapid): Assigned by PCI-SIG for subsystem capability ID.
MSI Capability (msicapid, msinxtptr, msimsgctl): Details the MSI capability ID, next pointer, and control settings for MSI interrupts.
PCI Express Capability (pxpcapid, pxpnxtptr, pxpcap): Provides PCI Express capability ID and related settings.

Device Capabilities and Control:

Device Capabilities (devcap): Identifies device-specific information, including slot implementation and device port type.
Device Control (devctrl): Manages device control settings, such as extended tag field support and maximum payload size.

Clock Configuration: The processor's clock configuration is determined by the 'slot_clock_configuration' bit, which indicates whether the processor and the device on the other end of the link share the same crystal oscillator (xtal). A value of '1' means they share the same xtal, while '0' indicates different xtals are used. This setting is typically configured by the BIOS based on board clock routing and must be set to '1' in DMI mode operation on Device#0.

PCI Express Slot Capabilities: The 'sltcap' register identifies the PCI Express slot capabilities, including link training status, negotiated link width, and current link speed. The link training status indicates whether the Link Training and Status State Machine (LTSSM) is in recovery/configuration state. The negotiated link width shows the width of the PCI Express link after training, with possible values of x1, x2, x4, x8, and x16 for Device#1-2, and x1, x2, and x4 for Device#0.

Slot Control and Status: The 'sltcon' and 'sltsts' registers manage and report the status of PCI Express slot operations, such as hot-plug capabilities, power control, and presence detection. The slot control register allows for enabling hot-plug interrupts, power control, and attention indicators. The slot status register provides information on power faults, attention button presses, and presence detection changes.

Hot-Plug Capabilities: The document details various hot-plug capabilities, including support for hot-plug operations, surprise hot-plug events, and the presence of indicators and sensors. These capabilities are configured by the BIOS based on system design and are crucial for managing hot-plug operations in PCI Express slots.

Electromechanical Interlock and Indicators: The presence of electromechanical interlocks, power indicators, and attention indicators is determined by specific bits in the configuration registers. These features are used to manage the physical and electrical state of the PCI Express slots and are controlled by the BIOS.

Overview: This document provides detailed technical specifications and configuration registers for Integrated I/O (IIO) in PCI Express* systems. It outlines various control and status registers, their bit attributes, default values, and descriptions.

Key Sections:

Configuration Registers: The document details several configuration registers, including root control, root capabilities, and root status. Each register is associated with specific bus, device, and function numbers, and has a unique offset.
Bit Descriptions: Each register contains multiple bits with specific attributes (e.g., Read-Write, Read-Only) and default values. The document explains the purpose of each bit, such as enabling error notifications, controlling interrupt generation, and managing completion timeouts.
Error Handling: The document describes how the system handles different types of errors (fatal, non-fatal, and correctable) and the role of internal IIO core error logic in escalating these errors.
Link Capabilities and Control: It outlines the supported link speeds and the mechanisms for controlling link compliance and speed adjustments. Specific bits are used to manage de-emphasis levels and compliance testing.
Power Management Events (PME): The document explains how PME messages are handled, including the indication of pending PMEs and the process for clearing PME status bits.

Critical Information:

Error Notification: System error notifications can be generated for fatal, non-fatal, and correctable errors, with options for both system errors and MSI/INTx interrupts.
Completion Timeout: The document provides detailed encoding for completion timeout values, allowing system software to modify timeout ranges for transactions.
Link Speed Management: The document specifies how link speeds are supported and managed, including the impact of hardware settings like the Gen3OFF fuse.

Conclusion: This document serves as a comprehensive guide for configuring and managing IIO in PCI Express* systems, with a focus on error handling, power management, and link capabilities.

Overview: This document provides detailed information on the Integrated I/O (IIO) Configuration Registers, focusing on error handling and performance control within a PCI Express environment. It outlines various registers, their functions, and the significance of different error types and statuses.

1. Error Severity and Status Registers:

Uncorrectable Error Severity (uncerrsev): Indicates the severity of uncorrectable errors.
Correctable Error Status (corerrsts): Identifies the status of correctable errors detected by the PCI Express port.
Correctable Error Mask (corerrmsk): Masks correctable errors from being signaled.
Advanced Error Capabilities and Control Register (errcap): Manages advanced error capabilities.

2. Error Command and Status Registers:

Root Port Error Command (rperrcmd): Controls behavior upon detection of errors.
Root Port Error Status (rperrsts): Reports the status of error messages received by the Root Complex and errors detected by the Root Port.
Error Source Identification (errsid): Logs the Requestor ID of the source when an error message is received.

3. Performance Control and Status Registers:

Performance Control and Status Register 0 (perfctrlsts_0): Manages performance-related settings such as outstanding requests and flow control.
Performance Control and Status Register 1 (perfctrlsts_1): Further controls performance parameters.

4. Miscellaneous Control and Status Registers:

MISC Control and Status Register 0 (miscctrlsts_0): Includes settings for TLP Processing Hint, DCA Requester ID Override, and other miscellaneous controls.
MISC Control and Status Register 1 (miscctrlsts_1): Manages system error settings and other miscellaneous controls.

Key Parameters and Recommendations:

Registers are categorized by type, port ID, bus, device, function, and offset.
Each register has specific bits with attributes such as Read/Write (RW), Read-Only (RO), and Read-Write-Set (RWS).
Default values are provided for each bit, indicating the initial state of the register.
Recommendations for BIOS settings are included, particularly for performance optimization and error handling.

Virtual Channel (VC) Management:
- The VC Enable bit indicates whether a Virtual Channel is enabled or disabled. A '1' indicates enabled, and a '0' indicates disabled. The VC Negotiation Pending bit must be cleared to confirm VC enablement.
- BIOS requirements for VC management include setting VC Enable bits in both components on a link to enable a VC, ensuring no traffic uses a VC when disabling it, and fully disabling a VC before re-enabling it.

Traffic Class Mapping:
- Traffic Class 7 is always routed to VCm, while Traffic Class 0 is always routed to VC0. The mapping of other Traffic Classes to VC resources is indicated by specific bits.

VC Resource Status and Control:
- The DMI VCP Resource Status and DMI VCM Resource Capability sections report the status and capabilities of VC resources, including negotiation status and credit throttling.
- The VC Negotiation Pending bit indicates whether the VC negotiation process is complete.

Credit Throttling:
- Credit throttling controls the number of credits withheld for posted and non-posted requests for VC1, VCp, and VCm.

Device Configuration Registers:
- The document details various configuration registers for Integrated I/O (IIO) devices, including vendor and device identification numbers, command and status registers, and capability pointers.
- Specific registers control aspects like cacheline size, multifunction device status, and PCI Express capabilities.

BIOS and Software Requirements:
- Software must ensure VC negotiation is complete before using a VC and must manage traffic class mappings and credit throttling appropriately.
- BIOS must adhere to specific requirements for enabling and disabling VCs, ensuring no traffic is present during these operations.

PCI Express Capability Structure: This section outlines the versioning and compliance requirements for PCI Express and DMA devices, specifically focusing on the configuration of the PCI Express capability structure. It includes details on the configuration registers and their offsets, attributes, and default values.

MMCFG Base and Limit: The document specifies the base and limit addresses for the MMCFG region, which are aligned to a 64MB boundary. It explains how access within this range is managed and the conditions under which the region is disabled.

TSEG Configuration: This section describes the base and limit addresses for the TSEG region, aligned to a 1MB boundary. It details how access to this region is handled and the implications of setting the base greater than the limit.

Generic Protected Memory Range: The document outlines the configuration for generic protected memory ranges, including base and limit addresses. It explains how these ranges protect memory from inbound DMA accesses and their relationship with Intel VT-d specifications.

Memory Address Configuration: Various sections detail the configuration of memory addresses, including TOLM, TOHM, and non-coherent memory base and limit addresses. These configurations determine how memory transactions are directed and managed.

Intel Management Engine (ME) Memory Configuration: This part specifies the base and limit addresses for the Intel ME non-coherent memory, explaining how these addresses are used to manage UMA range transactions.

Local MMIO Configuration: The document describes the configuration of local MMIO low and high base and limit addresses, detailing how these settings affect peer-to-peer transactions and coherent interface interactions.

Coherent Interface Protocol Control: This section covers the control settings for the coherent interface protocol, including write transaction management and socket ID configuration. It provides details on how these settings influence system behavior and data handling.

Specifications:

Maximum Handle Mask Value: IIO supports all 16 bits of handle being masked. However, the hardware does not consider the mask value during global interrupt entry invalidation.
Invalidation Unit Offset: Invalidation registers are located at offset 200h.
Snoop Control: Hardware supports the 1-setting of the SNP field in page-table entries for non-isoch Intel VT-d engine.
Pass Through: Supported by IIO, with defeaturing option for post-silicon bugs.
IA32 Extended Interrupt Mode: Supported by IIO.
Interrupt Remapping Support: Supported by IIO.
Device TLB Support: Supported for non-isoch Intel VT-d engine, with defeaturing option for post-silicon bugs.
Queued Invalidation Support: Supported by IIO.
Coherency Support: BIOS can write to indicate snoop or non-snoop for DMA/Interrupt table structures, expected to be set to 0 for Intel VT-d engine.

Procedures:

Translation Enable: Software must set up DMA-remapping structures, flush write buffers, set root-entry table pointer, perform global invalidation of context-cache and IOTLB, and set up fault log pointer if advanced fault logging is supported before enabling DMA-remapping hardware.
Set Root Table Pointer: Must be performed before enabling DMA remapping hardware. Requires global invalidation of context cache and IOTLB.
Queued Invalidation Enable: Software must ensure all prior invalidations are completed before enabling queued invalidations.
Interrupt Remapping Enable: Requires setup of interrupt-remapping structures and global invalidation of IOTLB.

Norms and Recommendations:

Ensure deterministic transaction boundaries when enabling/disabling remapping logic to handle in-flight transactions appropriately.
Update root table and interrupt remap table pointers only when necessary and ensure new structures provide the same remapping results as previous ones.

Fault Status:

Fault Record Index: Indicates the index of the fault recording register for the first pending fault.
Invalidation Timeout Error: Detected when Device-IOTLB invalidation completion times out.
Invalidation Completion Error: Occurs when an unexpected or invalid Device-IOTLB invalidation completion is received.
Invalidation Queue Error: Detected when there is an error associated with the invalidation queue.

Overview: This document provides detailed technical specifications and configurations for Intel VT-d (Virtualization Technology for Directed I/O) and Integrated I/O (IIO) Configuration Registers. It includes information on fault recording, interrupt handling, memory protection, and invalidation processes.

Fault Recording and Handling: The document describes the mechanism for detecting and recording faults in DMA-remap hardware units. It explains the use of fault recording registers and the conditions under which fault events are generated. The primary fault pending field indicates if there are pending faults, and the primary fault overflow bit signals an overflow in fault recording registers.

Interrupt Management: The document outlines how interrupt conditions are detected and managed. It details the roles of various fields such as fault_nonisoch_msgmsk and fault_nonisoch_msi_pend in controlling interrupt message requests and handling pending interrupts.

Memory Protection: The document specifies the configuration of protected memory regions using Intel VT-d. It describes the use of low and high protected DRAM regions to prevent unauthorized DMA accesses, ensuring that only Intel VT-d engine operations are allowed.

Invalidation Processes: The document covers the invalidation queue management, including the configuration of queue head and tail pointers. It explains the process for invalidating page-table entries and the conditions under which invalidation events trigger interrupts.

Configuration Registers: Detailed descriptions of various configuration registers are provided, including their offsets, bit attributes, and default values. These registers control aspects such as interrupt remapping, fault recording, and invalidation operations.

Key Parameters and Limitations: The document highlights critical parameters such as the alignment requirements for memory addresses and the constraints on DMA access to protected regions. It also specifies the conditions under which software can modify or clear certain fields.

Overview: This document provides detailed technical specifications and configuration registers for Integrated I/O (IIO) in a computing system. It includes information on IOTLB invalidation requests, device identification, and memory hot-plug capabilities.

IOTLB Invalidation: The document outlines the process for invalidating the I/O Translation Lookaside Buffer (IOTLB). It specifies the Invalidation Request Granularity (IIRG) with options for global, domain-selective, and page-selective invalidation. The Actual Invalidation Granularity (IAIG) is reported by hardware, indicating the level of invalidation performed.

Device Identification: The document details various configuration registers for device identification, including vendor and device identification numbers. It specifies the default values and attributes for each register, such as the vendor identification number (0x8086) and device identification number (0xe29).

Memory Hot-Plug Capabilities: The document describes the memory hot-plug control and capabilities, including the ability to enable SMI interrupts on hot-plug events. It outlines the configuration for memory channels and slot capabilities, including power and attention indicators, and electromechanical interlock controls.

Configuration Registers: The document provides a comprehensive list of configuration registers, detailing their offsets, bit attributes, default values, and descriptions. It includes information on MSI capabilities, memory hot-plug control, and slot control features.

Key Parameters and Limitations: The document highlights critical parameters such as the granularity of invalidation requests, device and vendor IDs, and memory hot-plug capabilities. It also notes limitations, such as unsupported features and reserved fields.

Overview: This document provides detailed information on the Integrated I/O (IIO) Configuration Registers, focusing on error severity levels, error mapping, and control registers. It outlines how errors are categorized, reported, and managed within the system.

Error Severity Levels: Errors are classified into three severity levels: Correctable (Level 0), Recoverable (Level 1), and Fatal (Level 2). Each error type is associated with a specific severity level, which can be programmed by software.

IIO Core Error Severity (iioerrsv): This register maps internal core errors to their respective severity levels. It is a sticky register, reset only by PWRGOOD.

Miscellaneous Error Severity (mierrsv): This register handles various error types, including overflow/underflow and master abort address errors, with severity levels locked by RSPLCK.

PCIe Error Severity Map (pcierrsv): This register allows remapping of PCI-E errors to IIO error severity levels, facilitating system event generation based on error severity.

System Error Event Map (sysmap): Maps detected error severity to system events, such as generating NMI or SMIPMI messages.

Viral Alert and Error Pin Control (viral, errpinctl): These registers manage viral alerts and configure error pins based on detected error severity. They allow for disabling error pin assertions or configuring them as general-purpose outputs.

Error Pin Status and Data (errpinsts, errpindat): Reflects the state of error pin assertions and provides data values for general-purpose output configurations.

VPP Control and Status (vppctl, vppsts): Defines control commands and status for PCA9555, including enabling VPP functions for root ports and managing VPP errors.

Global Error Status (gcerrst, gcferrst, gcnerrst, gnerrst): These registers indicate corrected, fatal, and non-fatal errors reported to the IIO global error logic, detailing specific error types and their status.

Key Parameters and Recommendations: - Error severity levels are crucial for determining system responses to errors. - Proper configuration of error pins and viral alerts is essential for effective error management. - Regular monitoring of error status registers can help in early detection and resolution of issues.

Overview: This document provides detailed information on the Integrated I/O (IIO) Configuration Registers, focusing on Device 5 Function 4. It includes specifications for various registers, their offsets, bit attributes, and default values.

I/O Interrupt Source Register 1 (iointsrc1): This register is responsible for managing interrupt sources. It includes a 21-bit field (bits 20:0) that specifies different interrupt sources, such as INTA Root Port Core and various ME and CB DMA interrupts.

Remote I/O Interrupt Count (ioremintcnt): This register tracks the number of remote interrupts received. It is a 32-bit register with a default value of 0x0.

Remote I/O GPE Count (ioremgpecnt): This register counts different types of remote GPEs, including HPGPEs, PMGPEs, and GPEs, each with an 8-bit field.

I/OxAPIC Configuration: The I/OxAPIC has a direct memory-mapped space used to access redirection table entries. It supports aligned Dword reads and writes, with specific offsets accessible via ABAR and MBAR registers.

Index and Window Registers: The Index Register selects which indirect register appears in the window register for manipulation. The Window Register is used for data transactions with indirect registers.

EOI Register: This register converts level interrupts to edge-triggered MSI interrupts. It clears the Remote_IRR bit for matching I/O Redirection Table entries.

APIC ID and Version Registers: These registers identify APICs in the system, though they are not used by operating systems anymore.

Redirection Table Low/High Registers (rtl/rth): These registers are used to construct MSI interrupts. They include fields for disabling flushing, masking interrupts, and specifying delivery modes and vector numbers.

Key Parameters and Limitations: - Only aligned Dword reads and writes are allowed in I/OxAPIC memory space. - Access beyond certain offsets returns all 0s. - Specific delivery modes and trigger modes are defined for interrupt handling.

Catalog excerpts

Intel® Core? i7 Processor for LGA2011 Socket: Datasheet, Vol. 2-1

Intel® Core™ i7 Processor Family for LGA2011 Socket Datasheet – Volume 2 of 2 Supporting Desktop Intel® Core™ i7-4960X Extreme Edition Processor Series for the LGA2011 Socket Supporting Desktop Intel® Core™ i7-49xx and i7-48xx Processor Series for the LGA2011 Socket

Open the catalog to page 1

Intel® Core? i7 Processor for LGA2011 Socket: Datasheet, Vol. 2-2

INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Legal Lines...

Open the catalog to page 2

Intel® Core? i7 Processor for LGA2011 Socket: Datasheet, Vol. 2-13

Revision History Revision Number 001 Initial release

Open the catalog to page 13

Intel® Core? i7 Processor for LGA2011 Socket: Datasheet, Vol. 2-14

(This page intentionally left blank)

Open the catalog to page 14

Intel® Core? i7 Processor for LGA2011 Socket: Datasheet, Vol. 2-15

Introduction This document is Volume 2 of 2 of the datasheet for the Intel® Core™ i7 processor family for LGA2011 Socket. Volume 2 provides register information for these processors. Volume 2 of 2 describes the Configuration Status Registers (CSRs) of each individual functional block in Uncore logic. The processor contains one or more PCI devices within each individual functional block. CSRs are the basic hardware elements that configure the Uncore logic to support various system topologies, memory configuration, and densities. The processor family contains one or more PCI devices within a single...

Open the catalog to page 15

Intel® Core? i7 Processor for LGA2011 Socket: Datasheet, Vol. 2-16

Document Terminology Processor Terminology (Sheet 1 of 2) Terminology Third generation Double Data Rate SDRAM memory technology that is the successor to DDR2 SDRAM Direct Memory Access Direct Media Interface 2 Digital Thermal Sensor Enhanced Intel® SpeedStep® Technology Intel technology that allows the operating system to reduce power consumption when performance is not needed. The Execute Disable bit allows memory to be marked as executable or nonexecutable–when combined with a supporting operating system. If code attempts to run in non-executable memory the processor raises an error to the...

Open the catalog to page 16

Intel® Core? i7 Processor for LGA2011 Socket: Datasheet, Vol. 2-17

Processor Terminology (Sheet 2 of 2) Terminology Power Control Unit Platform Environment Control Interface 64-bit, single-core or multi-core component (package) Processor Core The term “processor core” refers to silicon die itself which can contain multiple execution cores. Each execution core has an instruction cache, data cache, and 256KB L2 cache. All execution cores share the L3 cache. A unit of DRAM connecting four to eight devices in parallel. These devices are usually, but not always, mounted on a single side of a DDR3 DIMM. Processor interconnect between the different Uncore modules Indicate...

Open the catalog to page 17

Intel® Core? i7 Processor for LGA2011 Socket: Datasheet, Vol. 2-18

Related Documents Refer to the following documents for additional information. Processor Documents Document Document Number/ Location Intel® Core™ i7 Processor Family for the LGA2011 Socket Datasheet, Volume 1 Desktop Intel Core™ i7 Processor Family for the LGA2011 Thermal Mechanical Specification and Design Guide Intel® Core™ i7 Processor Family for the LGA2011 Socket Specification Update Intel® X79 Express Chipset Datasheet Intel® X79 Express Chipset Thermal Mechanical Specifications and Design Guide Advanced Configuration and Power Interface Specification 3.0 http://www.pcisig.com/ specifications...

Open the catalog to page 18

Intel® Core? i7 Processor for LGA2011 Socket: Datasheet, Vol. 2-19

Registers Overview and Configuration Process Registers Overview and Configuration Process This chapter covers • • • • Platform Configuration Structure Configuration Register Rules Register Terminology Notational Conventions Platform Configuration Structure The DMI2 physically connects the processor and the PCH. From a configuration standpoint the DMI2 is a logical extension of PCI Bus 0. DMI2 and the internal devices in the processor IIO and PCH logically constitute PCI Bus 0 to configuration software. As a result, all devices internal to the processor and the PCH appear to be on PCI Bus 0. Processor...

Open the catalog to page 19

Intel® Core? i7 Processor for LGA2011 Socket: Datasheet, Vol. 2-20

Registers Overview and Configuration Process • Device 0: DMI2 Root Port. Logically this appears as a PCI device residing on PCI Bus 0. Device 0 contains the standard PCI header registers, extended PCI configuration registers and DMI2 device specific configuration registers. • Device 1: PCI Express* Root Port 1a, 1b. Logically this appears as a “virtual” PCI-to-PCI bridge residing on PCI Bus 0 and is compliant with PCI Express* Local Bus Specification Revision 2.0. Device 1 contains the standard PCI Express*/PCI configuration registers including PCI Express* Memory Address Mapping registers. It...

Open the catalog to page 20

Intel® Core? i7 Processor for LGA2011 Socket: Datasheet, Vol. 2-21

Registers Overview and Configuration Process Processor Uncore Devices Map Bus = CPUBUSNO (1)* Power Control Unit (PCU) (Device 10, Function 0‐ 4) Integrated Memory Controller (Device 15 General Registers, TAD Rank and Timings, Device 16 Thermal Control and Test Registers) Performance Monitoring (Device 14,16,19) • Device 10: Processor Power Control Unit. Device 10, Function 0-4 contains the configurable PCU registers. • Device 11: Processor Interrupt Event Handling (UBox). Device 11, Function 0 contains the processor Interrupt Control Registers. Device 11, Function 3 contains the Semaphore...

Open the catalog to page 21

Intel® Core? i7 Processor for LGA2011 Socket: Datasheet, Vol. 2-22

Registers Overview and Configuration Process • Device 19: Processor Performance Monitoring and Ring. Device 19 Function 0 contains the processor ring to PCI Express agent. Device 19, Function 1 contains the processor Ring to PCI Express performance monitoring registers. Device 19, Function 4 -6 contains the processor performance monitoring registers. • Device 22: Processor Core Broadcast. Device 22 Function 1-2 contains the Caching agent broadcast configuration registers for the Memory Controller. Device 22 Function 0 contains the System Address Decode Registers. Configuration Register Rules...

Open the catalog to page 22

Intel® Core? i7 Processor for LGA2011 Socket: Datasheet, Vol. 2-23

Registers Overview and Configuration Process Device Mapping Each component in the processor is uniquely identified by a PCI bus address consisting of Bus Number, Device Number, and Function Number. Device configuration is based on the PCI Type 0 configuration conventions. All processor registers appear on the PCI bus assigned for the processor socket. Bus number is derived by the maximum bus range setting and processor socket number. Functions Specifically Handled by the Processor (Sheet 1 of 2) Register Group x4 Link from Processor to PCH Device 0 will work as a x4 PCI Express Port PCI Express...

Open the catalog to page 23

All Intel catalogs and technical brochures

Archived catalogs

*Prices are pre-tax. They exclude delivery charges and customs duties and do not include additional charges for installation or activation options. Prices are indicative only and may vary by country, with changes to the cost of raw materials and exchange rates.

Brand list