Document # 323252-002 Intel® Core™ i7-900 Desktop Processor Extreme Edition Series and Intel® Core™ i7-900 Desktop Processor Series on 32-nm Process Datasheet, Volume 1 July 2010

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Datasheet 7 Revision History § Revision Number Description Date 001 • Initial release March 2010 002 • Added Intel® Core™ i7-970 desktop processor series July 2010

Datasheet 9 Introduction 1 Introduction The Intel® Core™ i7-900 desktop processor Extreme Edition series and Intel® Core™ i7-900 desktop processor series on 32-nm process processor is intended for high performance, high-end desktop systems. Several architectural and microarchitectural enhancements have been added to this processor including six processor cores in the processor package and increased shared cache. The Intel® Core™ i7-900 desktop processor Extreme Edition series and and Intel® Core™ i7-970 desktop processor series on 32-nm process is a desktop multi-core processor with these key...

Introduction 10 Datasheet The processor supports all the existing Streaming SIMD Extensions 2 (SSE2), Streaming SIMD Extensions 3 (SSE3) and Streaming SIMD Extensions 4 (SSE4). The processor supports several Advanced Technologies: Intel® 64 Technology (Intel® 64), Enhanced Intel SpeedStep® Technology, Intel® Virtualization Technology (Intel® VT), Turbo Boost Technology, and Hyper-Threading Technology. 1.1 Terminology A ‘#’ symbol after a signal name refers to an active low signal, indicating a signal is in the active state when driven to a low level. For example, when RESET# is low, a reset has...

Datasheet 13 Electrical Specifications 2 Electrical Specifications 2.1 Intel® QuickPath Interconnect (Intel® QPI) Differential Signaling The processor provides an Intel QPI port for high speed serial transfer between other Intel QPI-enabled components. The Intel QPI port consists of two unidirectional links (for transmit and receive). Intel QPI uses a differential signalling scheme where pairs of opposite-polarity (D_P, D_N) signals are used. On-die termination (ODT) provided on the processor silicon and termination is to VSS. Intel chipsets also provide ODT; thus, eliminating the need to terminate...

Electrical Specifications 14 Datasheet condition from a running condition. Care must be taken in the baseboard design to ensure that the voltage provided to the processor remains within the specifications listed in Table 2-7. Failure to do so can result in timing violations or reduced lifetime of the processor. 2.3.1 VCC, VTTA, VTTD, VDDQ Decoupling Voltage regulator solutions need to provide bulk capacitance and the baseboard designer must assure a low interconnect resistance from the regulator to the LGA1366 socket. Bulk decoupling must be provided on the baseboard to handle large current swings....

Datasheet 15 Electrical Specifications 2.5 Voltage Identification (VID) The Voltage Identification (VID) specification for the processor is defined by the Voltage Regulator Down (VRD) 11.1 Design Guidelines. The voltage set by the VID signals is the reference voltage regulator output voltage to be delivered to the processor VCC pins. VID signals are CMOS push/pull drivers. Refer to Table 2-15 for the DC specifications for these signals. The VID codes will change due to temperature and/or current load changes in order to minimize the power of the part. A voltage range is provided in Table 2-7....

Electrical Specifications 18 Datasheet 2.6 Reserved or Unused Signals All Reserved (RSVD) signals must remain unconnected. Connection of these signals to VCC, VTTA, VTTD, VDDQ, VCCPLL, VSS, or to any other signal (including each other) can result in component malfunction or incompatibility with future processors. See Chapter 4 for a land listing of the processor and the location of all Reserved signals. For reliable operation, always connect unused inputs or bi-directional signals to an appropriate signal level, except for unused integrated memory controller inputs, outputs, and bi-directional...

Datasheet 19 Electrical Specifications 2.7 Signal Groups Signals are grouped by buffer type and similar characteristics as listed in Table 2-3. The buffer type indicates which signaling technology and specifications apply to the signals. All the differential signals, and selected DDR3 and Control Sideband signals have On- Die Termination (ODT) resistors. There are some signals that do not have ODT and need to be terminated on the board. The signals that have ODT are listed in Table 2-4. Table 2-3. Signal Groups (Sheet 1 of 2) Signal Group Type Signals1,2 System Reference Clock Differential Clock...

Electrical Specifications 20 Datasheet Note: 1. Unless otherwise specified, signals have ODT in the package with 50 Ă pulldown to VSS. 2. PREQ#, BPM[7:0], TDI, TMS and BCLK_ITP_D[N/P] have ODT in package with 35 Ă pullup to VTT. 3. VCCPWRGOOD, VDDPWRGOOD, and VTTPWRGOOD have ODT in package with a 10 kĂ to 20 kĂ pulldown to VSS. 4. TRST# has ODT in package with a 1 kĂ to 5 kĂ pullup to VTT. 5. All DDR signals are terminated to VDDQ/2 6. DDR{0/1/2} refers to DDR3 Channel 0, DDR3 Channel 1, and DDR3 Channel 2. 7. While TMS and TDI do not have On-Die Termination, these signals are weakly pulled...

Datasheet 21 Electrical Specifications 2.9 Platform Environmental Control Interface (PECI) DC Specifications PECI is an Intel proprietary interface that provides a communication channel between Intel processors and chipset components to external thermal monitoring devices. The processor contains a Digital Thermal Sensor (DTS) that reports a relative die temperature as an offset from Thermal Control Circuit (TCC) activation temperature. Temperature sensors located throughout the die are implemented as analog-to-digital converters calibrated at the factory. PECI provides an interface for external...