Intel® 6 Series Chipset and Intel® C200 Series Chipset Datasheet
934Pages

Document Number: 324645-004 Intel® 6 Series Chipset and Intel® C200 Series Chipset Datasheet April 2011

2 Datasheet INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL’S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY...

Datasheet 37 Revision History Revision Description Date 001 • Initial Release January 2011 002 • Added the Intel Q67, B65, H61, QM67, UM67, and QS67 Chipset • Chapter 1 — Updated Table 1-1 — Updated following sub-sections in Section 1.2.1 - Intel® Active Management Technology (Intel® AMT) - SOL Function - KVM (new) - IDE-R Function • Chapter 5 — Updated Table 5-22, 5-23, and 5-29. • Chapter 6 — Added SFF Top View Ballout figures in Section 6.3. • Chapter 8 — Updated Table 8-1 to add Tj for Mobile. • Chapter 9 — Updated Table 9-3, Variable I/O Decode Ranges • Chapter 10 — Updated Section...

38 Datasheet Platform Controller Hub Features ƒÞ Direct Media Interface — NEW: Up to 20 Gb/s each direction, full duplex — Transparent to software ƒÞ PCI Express* — Up to eight PCI Express root ports — NEW: Supports PCI Express Rev 2.0 running at up to 5.0 GT/s — Ports 1-4 and 5-8 can independently be configured to support eight x1s, two x4s, two x2s and four x1s, or one x4 and four x1 port widths — Module based Hot-Plug supported (that is, ExpressCard*) ƒÞ Integrated Serial ATA Host Controller — Up to six SATA ports — NEW: Data transfer rates up to 6.0 Gb/s (600 MB/s) on up to two ports —...

Datasheet 39 Note: Not all features are available on all PCH SKUs. See Section 1.3 for more details. § § ƒÞ External Glue Integration — Integrated Pull-down and Series resistors on USB ƒÞ Enhanced DMA Controller — Two cascaded 8237 DMA controllers — Supports LPC DMA ƒÞ PCI Bus Interface (not available on all SKUs) — Supports PCI Rev 2.3 Specification at 33 MHz — Four available PCI REQ/GNT pairs — Support for 64-bit addressing on PCI using DAC protocol ƒÞ SMBus — Interface speeds of up to 100 kbps — Flexible SMBus/SMLink architecture to optimize for ASF — Provides independent manageability...

Datasheet 41 Introduction 1 Introduction 1.1 About This Manual This document is intended for Original Equipment Manufacturers and BIOS vendors creating Intel® 6 Series Chipset and Intel® C200 Series Chipset based products (See Section 1.3 for currently defined SKUs). Note: Throughout this document, Platform Controller Hub (PCH) is used as a general term and refers to all Intel 6 Series Chipset and Intel C200 Series Chipset SKUs, unless specifically noted otherwise. Note: Throughout this document, the terms “Desktop” and “Desktop Only” refer to information that is applicable only to the...

Introduction 42 Datasheet Chapter 1, “Introduction” Chapter 1 introduces the PCH and provides information on manual organization and gives a general overview of the PCH. Chapter 2, “Signal Description” Chapter 2 provides a block diagram of the PCH and a detailed description of each signal. Signals are arranged according to interface and details are provided as to the drive characteristics (Input/Output, Open Drain, etc.) of all signals. Chapter 3, “PCH Pin States” Chapter 3 provides a complete list of signals, their associated power well, their logic level in each suspend state, and their...

Datasheet 43 Introduction Chapter 5, “Functional Description” Chapter 5 provides a detailed description of the functions in the PCH. Chapter 6, “Ballout Definition” Chapter 6 provides the ball assignment table and the ball-map for the Desktop, Mobile and Mobile SFF packages. Chapter 7, “Package Information” Chapter 7 provides drawings of the physical dimensions and characteristics of the Desktop, Mobile and Mobile SFF packages. Chapter 8, “Electrical Characteristics” Chapter 8 provides all AC and DC characteristics including detailed timing diagrams. Chapter 9, “Register and Memory Mapping”...

Introduction 44 Datasheet Chapter 19, “PCI Express* Configuration Registers” Chapter 19 provides a detailed description of registers that reside in the PCI Express controller. This controller resides at Device 28, Functions 0 to 7 (D28:F0-F7). Chapter 20, “High Precision Event Timer Registers” Chapter 20 provides a detailed description of registers that reside in the multimedia timer memory mapped register space. Chapter 21, “Serial Peripheral Interface (SPI)” Chapter 21 provides a detailed description of registers that reside in the SPI memory mapped register space. Chapter 22, “Thermal...

Datasheet 45 Introduction • Intel® Anti-Theft Technology (Intel® AT) • JTAG Boundary Scan support The PCH incorporates a variety of PCI devices and functions separated into logical devices, as shown in Table 9-1. Note: Not all functions and capabilities may be available on all SKUs. Please see Section 1.3 for details on SKU feature availability. 1.2.1 Capability Overview The following sub-sections provide an overview of the PCH capabilities. Direct Media Interface (DMI) Direct Media Interface (DMI) is the chip-to-chip connection between the processor and PCH. This high-speed interface...

Introduction 46 Datasheet Serial ATA (SATA) Controller The PCH has two integrated SATA host controllers that support independent DMA operation on up to six ports and supports data transfer rates of up to 6.0 Gb/s (600 MB/s) on up to two ports while all ports support rates up to 3.0 Gb/s (300 MB/s) and up to 1.5 Gb/s (150 MB/s). The SATA controller contains two modes of operation— a legacy mode using I/O space, and an AHCI mode using memory space. Software that uses legacy mode will not have AHCI capabilities. The PCH supports the Serial ATA Specification, Revision 3.0. The PCH also supports...