i7-lga2011
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i7-lga2011
Product catalog summary
Introduction
This document is the second volume of the datasheet for the Intel® Core™ i7 Processor Family designed for the LGA2011 socket. It supports the Intel® Core™ i7-4960X Extreme Edition and other i7-49xx and i7-48xx series processors. The document includes legal disclaimers, emphasizing that Intel provides no warranty for the use of its products in mission-critical applications and that specifications may change without notice.
This document is the second volume of the datasheet for the Intel® Core™ i7 Processor Family designed for the LGA2011 socket. It supports the Intel® Core™ i7-4960X Extreme Edition and other i7-49xx and i7-48xx series processors. The document includes legal disclaimers, emphasizing that Intel provides no warranty for the use of its products in mission-critical applications and that specifications may change without notice.
Registers Overview and Configuration Process
This section details the platform configuration structure, including processor IIO and uncore devices. It explains configuration register rules, such as CSR access, PCI bus numbers, and device mapping. Memory-mapped I/O registers and register terminology are also covered.
This section details the platform configuration structure, including processor IIO and uncore devices. It explains configuration register rules, such as CSR access, PCI bus numbers, and device mapping. Memory-mapped I/O registers and register terminology are also covered.
Integrated Memory Controller (IMC) Configuration Registers
The document provides an extensive list of configuration registers for the IMC, detailing various devices and functions. It includes descriptions of registers like pxpcap, mcmtr, and mh_maincntl, among others. Each register's purpose and configuration options are outlined to assist in system setup and optimization.
The document provides an extensive list of configuration registers for the IMC, detailing various devices and functions. It includes descriptions of registers like pxpcap, mcmtr, and mh_maincntl, among others. Each register's purpose and configuration options are outlined to assist in system setup and optimization.
Key Considerations
- Intel's legal disclaimers highlight the absence of warranties for certain applications and the potential for changes in specifications.
- The document emphasizes the importance of consulting Intel's resources for the latest specifications and errata.
- Overclocking and virtualization technologies are discussed, with warnings about potential impacts on system stability and performance.
- Intel's legal disclaimers highlight the absence of warranties for certain applications and the potential for changes in specifications.
- The document emphasizes the importance of consulting Intel's resources for the latest specifications and errata.
- Overclocking and virtualization technologies are discussed, with warnings about potential impacts on system stability and performance.
Conclusion
This datasheet is a technical guide for configuring and optimizing Intel® Core™ i7 processors for the LGA2011 socket. It provides detailed information on register configurations and system requirements, essential for developers and engineers working with these processors.
This datasheet is a technical guide for configuring and optimizing Intel® Core™ i7 processors for the LGA2011 socket. It provides detailed information on register configurations and system requirements, essential for developers and engineers working with these processors.
Document Terminology
The document includes a comprehensive glossary of terms related to processor technology, such as DDR3, DMA, DMI2, and Intel® Turbo Boost Technology. Each term is defined to aid understanding of the technical content.
The document includes a comprehensive glossary of terms related to processor technology, such as DDR3, DMA, DMI2, and Intel® Turbo Boost Technology. Each term is defined to aid understanding of the technical content.
Related Documents
A list of related documents is provided for further reference, including datasheets, thermal mechanical specifications, and design guides for the Intel® Core™ i7 Processor Family and Intel® X79 Express Chipset.
A list of related documents is provided for further reference, including datasheets, thermal mechanical specifications, and design guides for the Intel® Core™ i7 Processor Family and Intel® X79 Express Chipset.
Processor Uncore Devices Map
This section outlines the mapping of various processor uncore devices, including the Integrated Memory Controller, Processor Core Broadcast, CPU Interrupt Handling, CPU Home Agents, Performance Monitoring, Power Control Unit, and DDRIO. Each device is associated with specific bus numbers and functions, which are crucial for configuration and performance monitoring.
This section outlines the mapping of various processor uncore devices, including the Integrated Memory Controller, Processor Core Broadcast, CPU Interrupt Handling, CPU Home Agents, Performance Monitoring, Power Control Unit, and DDRIO. Each device is associated with specific bus numbers and functions, which are crucial for configuration and performance monitoring.
Configuration Register Rules
The processor supports different types of configuration registers, including PCI Configuration Registers, Machine Specific Registers, and Memory-Mapped I/O Registers. The document explains how these registers are accessed and the rules governing their use, such as the use of the bus:device:function number concept.
The processor supports different types of configuration registers, including PCI Configuration Registers, Machine Specific Registers, and Memory-Mapped I/O Registers. The document explains how these registers are accessed and the rules governing their use, such as the use of the bus:device:function number concept.
Unimplemented Devices and Device Hiding
The document discusses the handling of unimplemented devices and functions, noting that configuration reads to these will return all ones, emulating a master abort response. It also describes the mechanism for hiding devices from host configuration software using the DEVHIDE register.
The document discusses the handling of unimplemented devices and functions, noting that configuration reads to these will return all ones, emulating a master abort response. It also describes the mechanism for hiding devices from host configuration software using the DEVHIDE register.
Memory-Mapped I/O Registers
This section explains the role of memory-mapped I/O registers in the PCI standard, noting that they are typically where most driver programming occurs. Access to these registers is accomplished through processor reads and writes.
This section explains the role of memory-mapped I/O registers in the PCI standard, noting that they are typically where most driver programming occurs. Access to these registers is accomplished through processor reads and writes.
Integrated Memory Controller (IMC) Configuration Registers Overview
The document provides detailed technical specifications and configuration registers for the Integrated Memory Controller (IMC) with a focus on TSOD sensors, SMBus configurations, and DIMM temperature management.
The document provides detailed technical specifications and configuration registers for the Integrated Memory Controller (IMC) with a focus on TSOD sensors, SMBus configurations, and DIMM temperature management.
TSOD Sensor Configuration
The document outlines the bit configuration for TSOD sensors across different channel slots. Bits 7 and 3 must be programmed to zero as upper and lower channel slot #3 are not supported. Bits 6 to 0 indicate the presence of TSOD sensors in various slots.
The document outlines the bit configuration for TSOD sensors across different channel slots. Bits 7 and 3 must be programmed to zero as upper and lower channel slot #3 are not supported. Bits 6 to 0 indicate the presence of TSOD sensors in various slots.
DIMM Memory Technology
The document describes the DIMM Memory Technology registers, including rank disable controls, DIMM population status, and DDR3 width and density settings. It also covers the configuration for rank and address width.
The document describes the DIMM Memory Technology registers, including rank disable controls, DIMM population status, and DDR3 width and density settings. It also covers the configuration for rank and address width.
Temperature Management
The document provides configurations for DIMM temperature thresholds and hysteresis values. It includes settings for thermal throttling limits and the initiation of system interrupts based on temperature thresholds. The document also details the DIMM temperature offset and event assertion settings for temperature-related events.
The document provides configurations for DIMM temperature thresholds and hysteresis values. It includes settings for thermal throttling limits and the initiation of system interrupts based on temperature thresholds. The document also details the DIMM temperature offset and event assertion settings for temperature-related events.
Critical Parameters
Key parameters include the TSOD poll rate, SMBus clock period, DIMM rank disable settings, and temperature thresholds for thermal management. The document emphasizes the importance of configuring these parameters correctly to ensure optimal performance and prevent data loss.
Key parameters include the TSOD poll rate, SMBus clock period, DIMM rank disable settings, and temperature thresholds for thermal management. The document emphasizes the importance of configuring these parameters correctly to ensure optimal performance and prevent data loss.
Event Assertions and Interrupts
Each event assertion triggers a configurable interrupt, either MEMHOT# only or both SMI and MEMHOT#, as defined in bit 30 of CHN_TEMP_CFG.
Each event assertion triggers a configurable interrupt, either MEMHOT# only or both SMI and MEMHOT#, as defined in bit 30 of CHN_TEMP_CFG.
DIMM Temperature Management
Current DIMM temperature for thermal throttling. The temperature can be written to for testing when unlocked. The valid range is 0 to 127°C. The default is set to 85°C to ensure refresh during S3 resume or warm-reset.
Current DIMM temperature for thermal throttling. The temperature can be written to for testing when unlocked. The valid range is 0 to 127°C. The default is set to 85°C to ensure refresh during S3 resume or warm-reset.
Power Throttling
Defines the maximum number of transactions allowed during a 1 µsec throttling timeframe. Enables power throttling for the DIMM.
Defines the maximum number of transactions allowed during a 1 µsec throttling timeframe. Enables power throttling for the DIMM.
Timing Constraints
Defines various DDR3 timing constraints such as T_RAS, T_CWL, T_CL, T_RP, and T_RCD.
Defines various DDR3 timing constraints such as T_RAS, T_CWL, T_CL, T_RP, and T_RCD.
Integrated Memory Controller (IMC) Configuration Registers Overview
This section describes the MR0 shadow register configuration, which is programmed by the BIOS for all DIMMs in a channel. The iMC hardware dynamically issues MRS to MR0 to control fast and slow exit PPD. Address bits A[11:0] are defined by this register, while A15:A13 are always zero.
This section describes the MR0 shadow register configuration, which is programmed by the BIOS for all DIMMs in a channel. The iMC hardware dynamically issues MRS to MR0 to control fast and slow exit PPD. Address bits A[11:0] are defined by this register, while A15:A13 are always zero.
Page Closing Policy
The document outlines a page closing policy aimed at balancing Premature Page Closes (PPCs) and Overdue Page Closes (OPCs) to minimize costly Page Misses. The policy tracks PPCs and OPCs over a configurable window and adjusts page closing times based on thresholds.
The document outlines a page closing policy aimed at balancing Premature Page Closes (PPCs) and Overdue Page Closes (OPCs) to minimize costly Page Misses. The policy tracks PPCs and OPCs over a configurable window and adjusts page closing times based on thresholds.
RPQ Age Counter
This counter tracks the age of non-isoch transactions and promotes them to the next priority level once a configured value is reached. The BIOS must set this field to a non-zero value before enabling MCMTR.NORMAL.
This counter tracks the age of non-isoch transactions and promotes them to the next priority level once a configured value is reached. The BIOS must set this field to a non-zero value before enabling MCMTR.NORMAL.
Page Mode Configuration
The document describes three modes: Closed Page Mode, Open Page Mode, and Adaptive Open Mode, controlled by MCMTR.CLOSE_PG and ADAPT_PG_CLSE settings.
The document describes three modes: Closed Page Mode, Open Page Mode, and Adaptive Open Mode, controlled by MCMTR.CLOSE_PG and ADAPT_PG_CLSE settings.
Timing Parameters
Various timing parameters such as T_STAB, T_MRD, T_CKEV, and T_CKOFF are detailed, including their default values and functions. T_STAB ensures DCLK stability before device access, while T_MRD defines command word delays.
Various timing parameters such as T_STAB, T_MRD, T_CKEV, and T_CKOFF are detailed, including their default values and functions. T_STAB ensures DCLK stability before device access, while T_MRD defines command word delays.
Corrected Error Counters
The document provides details on corrected error counters per rank, including overflow conditions and thresholds. These counters are crucial for error management and are reset by BIOS.
The document provides details on corrected error counters per rank, including overflow conditions and thresholds. These counters are crucial for error management and are reset by BIOS.
Device Tagging
Device tagging for SDDC is explained, allowing for substitution of failing devices with parity from other devices. The document warns about potential errors in lock-step channel configurations.
Device tagging for SDDC is explained, allowing for substitution of failing devices with parity from other devices. The document warns about potential errors in lock-step channel configurations.
Overview
The document provides detailed technical specifications and configurations for various components within a system, focusing on memory controllers, processor utility boxes, and power controller units. It includes information on error handling, interrupt configurations, and power management.
The document provides detailed technical specifications and configurations for various components within a system, focusing on memory controllers, processor utility boxes, and power controller units. It includes information on error handling, interrupt configurations, and power management.
DDDC and SDDC Configuration
DDDC (Double Device Data Correction) and SDDC (Single Device Data Correction) are supported on certain systems, allowing for faster sparing with SDDC substitution. The Fail Device ID captures the ID of a failed device upon successful correction, with a valid range of 0-35 for x4 devices.
DDDC (Double Device Data Correction) and SDDC (Single Device Data Correction) are supported on certain systems, allowing for faster sparing with SDDC substitution. The Fail Device ID captures the ID of a failed device upon successful correction, with a valid range of 0-35 for x4 devices.
Integrated Memory Controller (IMC) Configuration
Details on various registers and their functions, including device IDs, command statuses, and configuration settings.
Details on various registers and their functions, including device IDs, command statuses, and configuration settings.
Processor Utility Box (UBOX) Registers
Handles non-mainstream flows such as register accesses and interrupt flows. Includes configuration for node IDs, interrupt control, and error status registers.
Handles non-mainstream flows such as register accesses and interrupt flows. Includes configuration for node IDs, interrupt control, and error status registers.
Power Controller Unit (PCU) Registers
Reports thermal status and manages power settings for the system. Includes registers for memory temperature reporting, accumulated bandwidth, and package power settings.
Reports thermal status and manages power settings for the system. Includes registers for memory temperature reporting, accumulated bandwidth, and package power settings.
Key Parameters and Settings
Temperature and power units are defined for accurate measurement and control. Settings for SMI (System Management Interrupt) generation and handling are detailed.
Temperature and power units are defined for accurate measurement and control. Settings for SMI (System Management Interrupt) generation and handling are detailed.
Conclusion
The document provides comprehensive technical details necessary for configuring and managing system components, focusing on error correction, power management, and interrupt handling.
The document provides comprehensive technical details necessary for configuring and managing system components, focusing on error correction, power management, and interrupt handling.
Thermal Monitor Reference Temperature (REF_TEMP)
This section describes the maximum junction temperature, also known as the throttle temperature, TCC activation temperature, or prochot temperature. It is the temperature at which the Thermal Monitor is activated. The firmware updates this register with a value calculated as 125 minus FUSETJMAXOFFSET.
This section describes the maximum junction temperature, also known as the throttle temperature, TCC activation temperature, or prochot temperature. It is the temperature at which the Thermal Monitor is activated. The firmware updates this register with a value calculated as 125 minus FUSETJMAXOFFSET.
Fan Temperature Target Offset (FAN_TEMP_TARGET_OFST)
Also known as T-Control, this indicates the relative offset from the Thermal Monitor Trip Temperature at which fans should be engaged. It is part of the configuration registers with specific bus, device, and function identifiers.
Also known as T-Control, this indicates the relative offset from the Thermal Monitor Trip Temperature at which fans should be engaged. It is part of the configuration registers with specific bus, device, and function identifiers.
Configuration Registers Overview
The document outlines two distinct CSR register spaces supported by the IIO Module: traditional PCI-defined configuration registers and MMIO space for Intel VT-d, RCRB, and I/OxAPIC runtime registers. It also discusses the handling of unimplemented devices/functions and registers, advising against software attempts to access these.
The document outlines two distinct CSR register spaces supported by the IIO Module: traditional PCI-defined configuration registers and MMIO space for Intel VT-d, RCRB, and I/OxAPIC runtime registers. It also discusses the handling of unimplemented devices/functions and registers, advising against software attempts to access these.
MMIO BARs in IIO
The document provides a table listing BDF:BAR# for various MMIO BARs in the IIO module, necessary for accessing MMIO registers over the message channel.
The document provides a table listing BDF:BAR# for various MMIO BARs in the IIO module, necessary for accessing MMIO registers over the message channel.
PCI vs. PCIe Device/Function
It differentiates between PCI and PCIe devices/functions, noting that PCI devices do not have a PCIe capability register set and do not decode offsets 100h and beyond.
It differentiates between PCI and PCIe devices/functions, noting that PCI devices do not have a PCIe capability register set and do not decode offsets 100h and beyond.
Device and Function Details
The document details various devices and functions, including their modes and port bifurcation, with tables illustrating the function numbers of active root ports based on port bifurcation.
The document details various devices and functions, including their modes and port bifurcation, with tables illustrating the function numbers of active root ports based on port bifurcation.
Integrated I/O Register Address Map
A comprehensive address map is provided, detailing register names, offsets, sizes, and associated devices/functions.
A comprehensive address map is provided, detailing register names, offsets, sizes, and associated devices/functions.
Specific Register Descriptions
The document describes specific registers such as vid, did, pcicmd, and pcists, including their types, offsets, bit attributes, defaults, and descriptions. These registers control various functionalities like interrupt disable, error reporting, and memory space enablement.
The document describes specific registers such as vid, did, pcicmd, and pcists, including their types, offsets, bit attributes, defaults, and descriptions. These registers control various functionalities like interrupt disable, error reporting, and memory space enablement.
Overview
This document provides detailed information on the Integrated I/O (IIO) Configuration Registers for PCI Express* interfaces. It outlines various error conditions, register settings, and configuration parameters essential for managing PCI Express* ports.
This document provides detailed information on the Integrated I/O (IIO) Configuration Registers for PCI Express* interfaces. It outlines various error conditions, register settings, and configuration parameters essential for managing PCI Express* ports.
Error Conditions
The document describes conditions that trigger specific error bits in the PCI Express* interface. For instance, bit 13 is set when a device receives a completion with an Unsupported Request or master abort status. Bit 12 is set for completer abort conditions on the primary interface.
The document describes conditions that trigger specific error bits in the PCI Express* interface. For instance, bit 13 is set when a device receives a completion with an Unsupported Request or master abort status. Bit 12 is set for completer abort conditions on the primary interface.
Register Descriptions
The document details several registers, including:
The document details several registers, including:
- Secondary Status Register: Contains bits for detecting parity errors, system errors, and master abort statuses.
- Primary Bus Number Register: Used to program the bus number on the primary side of the bridge.
- Memory Base and Limit Registers: Define memory-mapped I/O address ranges for PCI Express* ports.
- Prefetchable Memory Base and Limit Registers: Define prefetchable memory address ranges for 64-bit addresses.
Configuration Parameters
The document specifies various configuration parameters, such as:
The document specifies various configuration parameters, such as:
- Cacheline Size: Always set to 64B, though the register is RW for compatibility.
- I/O Base and Limit: Define the I/O address range for forwarding transactions.
- Memory Addressing: The document explains how memory base and limit registers are used to manage memory transactions.
Notes and Recommendations
The document includes notes on programming practices, such as ensuring consistency between registers and the importance of clearing specific bits before programming others.
The document includes notes on programming practices, such as ensuring consistency between registers and the importance of clearing specific bits before programming others.
Memory Address Alignment and Prefetchable Memory
The memory address range is aligned to a 1MB boundary, with the top of the range being one less than a 1MB boundary. The bottom 4 bits of the Prefetchable Memory Base and Limit registers indicate if the bridge supports 64-bit addresses. A value of 0h means only 32-bit addresses are supported, while 1h indicates 64-bit support, utilizing additional registers for the upper 32 bits. Setting the memory limit below the base disables the 64-bit range.
The memory address range is aligned to a 1MB boundary, with the top of the range being one less than a 1MB boundary. The bottom 4 bits of the Prefetchable Memory Base and Limit registers indicate if the bridge supports 64-bit addresses. A value of 0h means only 32-bit addresses are supported, while 1h indicates 64-bit support, utilizing additional registers for the upper 32 bits. Setting the memory limit below the base disables the 64-bit range.
Configuration Registers
Various configuration registers are detailed, including:
Various configuration registers are detailed, including:
- Capability Pointer (capptr): Points to the first capability structure, specifically the PCIe capability.
- Interrupt Line and Pin Registers (intl, intpin): These registers are not applicable for the devices mentioned.
- Bridge Control Register (bctrl): Controls features like hot reset, VGA I/O decoding, and error message forwarding.
- Subsystem Capability Identity (scapid) and Subsystem Vendor ID (svid): Assigned by PCI-SIG for subsystem identification.
- DMI Root Complex Register Block Base Address (dmircbar): Defines a 4KB block of memory address space, with specific conditions for enabling and updating.
- MSI Capability ID and Control (msicapid, msimsgctl): Details on MSI interrupt handling, including message allocation and enabling.
- PCI Express Capability Identity (pxpcapid): Provides the PCI Express capability ID.
- Device Capabilities (devcap): Identifies device-specific information, including slot implementation and error reporting capabilities.
Key Parameters and Limitations
Memory alignment and address support are critical for system configuration. Registers must be programmed with specific conditions, such as clearing the MSE bit before programming memory base and limit registers. Bridge control features like hot reset and VGA decoding have specific enabling conditions. MSI and PCI Express capabilities are detailed with specific register offsets and default values.
Memory alignment and address support are critical for system configuration. Registers must be programmed with specific conditions, such as clearing the MSE bit before programming memory base and limit registers. Bridge control features like hot reset and VGA decoding have specific enabling conditions. MSI and PCI Express capabilities are detailed with specific register offsets and default values.
Best Practices
Ensure proper alignment and configuration of memory addresses to avoid disabling features. Follow guidelines for enabling and updating configuration registers, especially in Intel TXT mode. Understand the implications of enabling features like hot reset and error message forwarding.
Ensure proper alignment and configuration of memory addresses to avoid disabling features. Follow guidelines for enabling and updating configuration registers, especially in Intel TXT mode. Understand the implications of enabling features like hot reset and error message forwarding.
Clock Configuration
The processor's clock configuration is determined by the 'slot_clock_configuration' bit, which indicates whether the processor and the device on the other end of the link share the same crystal oscillator (xtal). A value of 1 means they share the same xtal, while 0 means they use different xtals. This setting is typically configured by the BIOS based on board clock routing and is crucial for DMI mode operation on Device#0.
The processor's clock configuration is determined by the 'slot_clock_configuration' bit, which indicates whether the processor and the device on the other end of the link share the same crystal oscillator (xtal). A value of 1 means they share the same xtal, while 0 means they use different xtals. This setting is typically configured by the BIOS based on board clock routing and is crucial for DMI mode operation on Device#0.
PCI Express Slot Capabilities
The 'sltcap' register identifies specific slot capabilities for PCI Express. Key fields include 'link_training', which indicates the status of link training, and 'negotiated_link_width', which shows the negotiated width of the PCI Express link after training. The 'current_link_speed' field provides the current link speed.
The 'sltcap' register identifies specific slot capabilities for PCI Express. Key fields include 'link_training', which indicates the status of link training, and 'negotiated_link_width', which shows the negotiated width of the PCI Express link after training. The 'current_link_speed' field provides the current link speed.
Slot Control and Status
The 'sltcon' register manages slot control, including hot-plug capabilities. It includes fields like 'attention_button_present', which indicates if an attention button signal is routed to the IIO's hot-plug controller, and 'power_controller_control', which manages the power state of the slot. The 'sltsts' register provides status information, such as 'presence_detect_state', which indicates if a card/module is present in the slot.
The 'sltcon' register manages slot control, including hot-plug capabilities. It includes fields like 'attention_button_present', which indicates if an attention button signal is routed to the IIO's hot-plug controller, and 'power_controller_control', which manages the power state of the slot. The 'sltsts' register provides status information, such as 'presence_detect_state', which indicates if a card/module is present in the slot.
Hot-Plug Capabilities
Several fields define hot-plug support, such as 'hot_plug_capable', which indicates if a slot supports hot-plug operations, and 'hot_plug_surprise', which allows for device removal without prior notification. The 'hot_plug_interrupt_enable' field enables the generation of interrupts for hot-plug events.
Several fields define hot-plug support, such as 'hot_plug_capable', which indicates if a slot supports hot-plug operations, and 'hot_plug_surprise', which allows for device removal without prior notification. The 'hot_plug_interrupt_enable' field enables the generation of interrupts for hot-plug events.
Indicators and Sensors
The document details various indicators and sensors, including 'power_indicator_present' and 'attention_indicator_present', which indicate the presence of power and attention indicators, respectively. The 'mrl_sensor_present' field indicates if an MRL sensor is implemented for the slot.
The document details various indicators and sensors, including 'power_indicator_present' and 'attention_indicator_present', which indicate the presence of power and attention indicators, respectively. The 'mrl_sensor_present' field indicates if an MRL sensor is implemented for the slot.
Electromechanical Interlock
The 'electromechanical_interlock_present' field indicates if an electromechanical interlock is implemented, which is controlled by the Slot Control register. This feature is typically used for hotpluggable slots.
The 'electromechanical_interlock_present' field indicates if an electromechanical interlock is implemented, which is controlled by the Slot Control register. This feature is typically used for hotpluggable slots.
Integrated I/O (IIO) Configuration Registers Overview
Each bit in the configuration registers has specific attributes and default values that determine its behavior. For example, bits like mrl_sensor_changed, power_fault_detected, and attention_button_pressed are set by the Integrated I/O (IIO) when specific events occur and are cleared by software after processing.
Each bit in the configuration registers has specific attributes and default values that determine its behavior. For example, bits like mrl_sensor_changed, power_fault_detected, and attention_button_pressed are set by the Integrated I/O (IIO) when specific events occur and are cleared by software after processing.
PCI Express* Root Control
This section describes the control bits for PCI Express* Root, such as crsswvisen for enabling CRS software visibility, and pmeinten for controlling interrupt generation for PME messages. The SEFEEN, SENFEEN, and SECEEN bits manage system error notifications for fatal, non-fatal, and correctable errors, respectively.
This section describes the control bits for PCI Express* Root, such as crsswvisen for enabling CRS software visibility, and pmeinten for controlling interrupt generation for PME messages. The SEFEEN, SENFEEN, and SECEEN bits manage system error notifications for fatal, non-fatal, and correctable errors, respectively.
PCI Express* Root Capabilities and Status
The crs_software_visibility bit indicates the Root Port's capability to return CRS Completion Status. The pme_pending and pme_status bits manage PME message handling, indicating pending PMEs and the status of PME messages.
The crs_software_visibility bit indicates the Root Port's capability to return CRS Completion Status. The pme_pending and pme_status bits manage PME message handling, indicating pending PMEs and the status of PME messages.
Device Capabilities and Control
The tph_completer_supported bit indicates support for TLP Processing Hints. The ari_en bit shows support for Alternative RID Interpretation. Completion Timeout values are programmable, allowing system software to modify timeout ranges for transactions.
The tph_completer_supported bit indicates support for TLP Processing Hints. The ari_en bit shows support for Alternative RID Interpretation. Completion Timeout values are programmable, allowing system software to modify timeout ranges for transactions.
Link Capabilities and Control
The lnkspdvec field indicates supported link speeds, while compliance_de_emphasis and compliance_sos bits are used for compliance testing and debugging. The target_link_speed field sets an upper limit on link operational speed.
The lnkspdvec field indicates supported link speeds, while compliance_de_emphasis and compliance_sos bits are used for compliance testing and debugging. The target_link_speed field sets an upper limit on link operational speed.
Error Handling and Notifications
Error handling is managed through various bits that enable notifications for different types of errors. These notifications can be system errors or MSI/INTx interrupts, depending on the configuration.
Error handling is managed through various bits that enable notifications for different types of errors. These notifications can be system errors or MSI/INTx interrupts, depending on the configuration.
Configuration and Programming
Registers are configured in PCIe mode for specific devices and functions, with offsets provided for each configuration. The document details how to program these registers to achieve desired behaviors, such as enabling or disabling specific features.
Registers are configured in PCIe mode for specific devices and functions, with offsets provided for each configuration. The document details how to program these registers to achieve desired behaviors, such as enabling or disabling specific features.
Overview
This document provides detailed information on the Integrated I/O (IIO) Configuration Registers, focusing on error handling and performance control within a PCI Express environment. It outlines various registers, their functions, and the significance of different error types and statuses.
This document provides detailed information on the Integrated I/O (IIO) Configuration Registers, focusing on error handling and performance control within a PCI Express environment. It outlines various registers, their functions, and the significance of different error types and statuses.
Error Severity and Status Registers
Indicates the severity of uncorrectable errors. Identifies the status of correctable errors detected by the PCI Express port. Masks correctable errors from being signaled. Manages advanced error capabilities.
Indicates the severity of uncorrectable errors. Identifies the status of correctable errors detected by the PCI Express port. Masks correctable errors from being signaled. Manages advanced error capabilities.
Error Command and Status Registers
Controls behavior upon detection of errors. Reports the status of error messages received by the Root Complex and errors detected by the Root Port. Logs the Requestor ID of the source when an error message is received.
Controls behavior upon detection of errors. Reports the status of error messages received by the Root Complex and errors detected by the Root Port. Logs the Requestor ID of the source when an error message is received.
Performance Control and Status Registers
Manages performance-related settings such as outstanding requests and flow control. Further controls performance parameters.
Manages performance-related settings such as outstanding requests and flow control. Further controls performance parameters.
Miscellaneous Control and Status Registers
Includes settings for TLP Processing Hint, DCA Requester ID Override, and other miscellaneous controls. Manages system error settings and other miscellaneous controls.
Includes settings for TLP Processing Hint, DCA Requester ID Override, and other miscellaneous controls. Manages system error settings and other miscellaneous controls.
Key Parameters and Recommendations
Registers are categorized by their function, such as error severity, error status, and performance control. Each register has specific bits with attributes like Read/Write (RW), Read-Only (RO), and Read/Write Set (RWS), indicating how they can be manipulated. Default values are provided for each bit, which can be modified based on system requirements. Recommendations for BIOS settings are included, particularly for performance-related registers.
Registers are categorized by their function, such as error severity, error status, and performance control. Each register has specific bits with attributes like Read/Write (RW), Read-Only (RO), and Read/Write Set (RWS), indicating how they can be manipulated. Default values are provided for each bit, which can be modified based on system requirements. Recommendations for BIOS settings are included, particularly for performance-related registers.
Overview
This document provides detailed technical specifications and configuration registers for Integrated I/O (IIO) systems, focusing on Live Error Recovery (LER) capabilities and performance monitoring.
This document provides detailed technical specifications and configuration registers for Integrated I/O (IIO) systems, focusing on Live Error Recovery (LER) capabilities and performance monitoring.
Specifications
Points to the next capability in the extended configuration space. Set to 1h for this version of PCI Express logic. Assigned for advanced error reporting.
Points to the next capability in the extended configuration space. Set to 1h for this version of PCI Express logic. Assigned for advanced error reporting.
Live Error Recovery (LER)
LER is not supported; only Stop and Scream are available. Indicates an error causing the PCIe port to enter LER mode, disabling the link and aborting transactions. Indicates when the port has no pending packets after entering LER mode. Allows LER_SS Status to assert on error, enabling LER mode.
LER is not supported; only Stop and Scream are available. Indicates an error causing the PCIe port to enter LER mode, disabling the link and aborting transactions. Indicates when the port has no pending packets after entering LER mode. Allows LER_SS Status to assert on error, enabling LER mode.
Error Masks
Masks uncorrectable errors from being signaled as LER events. Specific to XP errors. Specific to root port errors.
Masks uncorrectable errors from being signaled as LER events. Specific to XP errors. Specific to root port errors.
Performance Monitoring
Performance monitor counter reset at the beginning of a sample period. Compares PMD to PMC values, affecting performance status. Contains high nibbles from PMD 36-bit counter register. Contains high nibbles from PMC 36-bit compare registers.
Performance monitor counter reset at the beginning of a sample period. Compares PMD to PMC values, affecting performance status. Contains high nibbles from PMD 36-bit counter register. Contains high nibbles from PMC 36-bit compare registers.
Configuration Registers
Identifies input enabling the counter, with options for local count, partner event status, and global debug events. Determines conditions for counter and event status reset. Defines usage of PMC register for comparison.
Identifies input enabling the counter, with options for local count, partner event status, and global debug events. Determines conditions for counter and event status reset. Defines usage of PMC register for comparison.
PCIe PerfMon Match Equation
Describes the logical combination of events for performance monitoring, including IO configuration and memory events.
Describes the logical combination of events for performance monitoring, including IO configuration and memory events.
Virtual Channel (VC) Management
The VC Enable bit indicates whether a Virtual Channel is enabled or disabled. A '1' indicates enabled, and a '0' indicates disabled. The VC Negotiation Pending bit must be cleared to confirm VC enablement. BIOS requirements for VC management include setting VC Enable bits in both components on a link to enable a VC, ensuring no traffic uses a VC when disabling it, and fully disabling a VC before re-enabling it.
The VC Enable bit indicates whether a Virtual Channel is enabled or disabled. A '1' indicates enabled, and a '0' indicates disabled. The VC Negotiation Pending bit must be cleared to confirm VC enablement. BIOS requirements for VC management include setting VC Enable bits in both components on a link to enable a VC, ensuring no traffic uses a VC when disabling it, and fully disabling a VC before re-enabling it.
Traffic Class Mapping
Traffic Class 7 is always routed to VCm, while Traffic Class 0 is always routed to VC0. The mapping of other Traffic Classes to VC resources is indicated by specific bits.
Traffic Class 7 is always routed to VCm, while Traffic Class 0 is always routed to VC0. The mapping of other Traffic Classes to VC resources is indicated by specific bits.
VC Resource Status and Capability
The DMI VCP Resource Status and Capability registers report the status and capabilities of Virtual Channels, including negotiation status and credit throttling. The VC Negotiation Pending bit indicates whether the VC negotiation process is complete.
The DMI VCP Resource Status and Capability registers report the status and capabilities of Virtual Channels, including negotiation status and credit throttling. The VC Negotiation Pending bit indicates whether the VC negotiation process is complete.
Credit Throttling
Credit throttling controls the number of credits withheld for posted and non-posted requests for different VCs.
Credit throttling controls the number of credits withheld for posted and non-posted requests for different VCs.
Device Configuration Registers
The document details various configuration registers for Integrated I/O (IIO) devices, including vendor and device identification numbers, command and status registers, and capability pointers. Specific bits in these registers are hardwired to certain values, indicating fixed functionalities or capabilities.
The document details various configuration registers for Integrated I/O (IIO) devices, including vendor and device identification numbers, command and status registers, and capability pointers. Specific bits in these registers are hardwired to certain values, indicating fixed functionalities or capabilities.
Overview
This document provides detailed technical specifications and configuration registers for Integrated I/O (IIO) in PCI Express and DMA devices. It includes information on memory address ranges, configuration settings, and control protocols.
This document provides detailed technical specifications and configuration registers for Integrated I/O (IIO) in PCI Express and DMA devices. It includes information on memory address ranges, configuration settings, and control protocols.
Specifications
Identified by version 2h, it ensures compliance with extended base registers. Defines the base and limit addresses for memory-mapped configuration space, aligned to 64MB boundaries. Specifies base and limit addresses for a memory region, aligned to 1MB boundaries, with specific address bits ignored.
Identified by version 2h, it ensures compliance with extended base registers. Defines the base and limit addresses for memory-mapped configuration space, aligned to 64MB boundaries. Specifies base and limit addresses for a memory region, aligned to 1MB boundaries, with specific address bits ignored.
Procedures
Protects memory from inbound DMA accesses, with base and limit addresses set at boot time and not changed thereafter. Defines base and limit addresses for non-coherent memory regions, preventing certain write commands.
Protects memory from inbound DMA accesses, with base and limit addresses set at boot time and not changed thereafter. Defines base and limit addresses for non-coherent memory regions, preventing certain write commands.
Norms and Recommendations
All base and limit addresses must be aligned to specified boundaries (64MB or 1MB) to ensure proper functionality. Protected Memory Regions should be used to prevent unauthorized access to critical memory areas, especially in PCIe segments.
All base and limit addresses must be aligned to specified boundaries (64MB or 1MB) to ensure proper functionality. Protected Memory Regions should be used to prevent unauthorized access to critical memory areas, especially in PCIe segments.
Key Parameters
Critical for defining memory regions and ensuring proper access control. Include settings for memory protection, coherent interface control, and internal bus numbers.
Critical for defining memory regions and ensuring proper access control. Include settings for memory protection, coherent interface control, and internal bus numbers.
Limitations
Certain address bits are ignored in comparisons, affecting how regions are defined. Many registers are set at boot time and do not change, limiting dynamic reconfiguration.
Certain address bits are ignored in comparisons, affecting how regions are defined. Many registers are set at boot time and do not change, limiting dynamic reconfiguration.
Best Practices
Verify all base and limit addresses are correctly set to prevent access issues. Use generic protected memory ranges to safeguard critical system areas from DMA accesses.
Verify all base and limit addresses are correctly set to prevent access issues. Use generic protected memory ranges to safeguard critical system areas from DMA accesses.
Technical Document Summary
The document outlines the mapping of Port IDs to TNID fields for various configurations. It specifies how Port IDs are assigned to different devices and functions, detailing the configurations for each port, such as x4, x8, or x16 lanes.
The document outlines the mapping of Port IDs to TNID fields for various configurations. It specifies how Port IDs are assigned to different devices and functions, detailing the configurations for each port, such as x4, x8, or x16 lanes.
Configuration Registers
The document provides detailed descriptions of various configuration registers within the Integrated I/O (IIO) system. It includes attributes like read/write permissions, default values, and specific functionalities such as enabling VGA accesses, controlling write ordering, and managing DMA protection.
The document provides detailed descriptions of various configuration registers within the Integrated I/O (IIO) system. It includes attributes like read/write permissions, default values, and specific functionalities such as enabling VGA accesses, controlling write ordering, and managing DMA protection.
DMA and Memory Protection
Details on DMA protected ranges are provided, including how memory is protected from DMA accesses. The document specifies the conditions under which protection is enabled or disabled and how it interacts with other protection mechanisms like Intel VT-d.
Details on DMA protected ranges are provided, including how memory is protected from DMA accesses. The document specifies the conditions under which protection is enabled or disabled and how it interacts with other protection mechanisms like Intel VT-d.
Intel VT-d Capabilities
The document describes the capabilities of Intel VT-d, including support for hardware-based draining, super pages, fault recording registers, and domain support. It also covers extended capabilities like advanced fault logging and memory range protection.
The document describes the capabilities of Intel VT-d, including support for hardware-based draining, super pages, fault recording registers, and domain support. It also covers extended capabilities like advanced fault logging and memory range protection.
Register Address Map
A comprehensive address map for the MMIO region of Device 5 Function 0 is included, detailing offsets and sizes for various registers related to Intel VT-d.
A comprehensive address map for the MMIO region of Device 5 Function 0 is included, detailing offsets and sizes for various registers related to Intel VT-d.
Recommendations and Best Practices
The document advises on setting specific bits for optimal performance and compatibility, such as leaving certain bits at default values unless specific conditions are met. It also highlights the importance of ensuring no active requests when modifying certain configurations.
The document advises on setting specific bits for optimal performance and compatibility, such as leaving certain bits at default values unless specific conditions are met. It also highlights the importance of ensuring no active requests when modifying certain configurations.
Specifications
IIO supports all 16 bits of handle being masked. However, the hardware does not consider the mask value during global interrupt entry invalidation. Invalidation registers are located at offset 200h. Hardware supports the 1-setting of the SNP field in page-table entries for non-isoch Intel VT-d engine. Supported by IIO, with defeaturing option for post-silicon bugs. Supported by IIO. Supported by IIO. Supported for non-isoch Intel VT-d engine, with defeaturing option for post-silicon bugs. Supported by IIO. Programmable for debug reasons, expected to be set to 0 for Intel VT-d engine.
IIO supports all 16 bits of handle being masked. However, the hardware does not consider the mask value during global interrupt entry invalidation. Invalidation registers are located at offset 200h. Hardware supports the 1-setting of the SNP field in page-table entries for non-isoch Intel VT-d engine. Supported by IIO, with defeaturing option for post-silicon bugs. Supported by IIO. Supported by IIO. Supported for non-isoch Intel VT-d engine, with defeaturing option for post-silicon bugs. Supported by IIO. Programmable for debug reasons, expected to be set to 0 for Intel VT-d engine.
Procedures
Software must set up DMA-remapping structures, flush write buffers, set root-entry table pointer, and perform global invalidation before enabling DMA-remapping hardware. Must be performed before enabling DMA remapping hardware. Requires global invalidation of context cache and IOTLB. Requires initialization of invalidation queue address register and completion of prior invalidations before enabling. Requires setup of interrupt-remapping structures and global invalidation of IOTLB before enabling.
Software must set up DMA-remapping structures, flush write buffers, set root-entry table pointer, and perform global invalidation before enabling DMA-remapping hardware. Must be performed before enabling DMA remapping hardware. Requires global invalidation of context cache and IOTLB. Requires initialization of invalidation queue address register and completion of prior invalidations before enabling. Requires setup of interrupt-remapping structures and global invalidation of IOTLB before enabling.
Norms and Recommendations
Ensure deterministic transaction boundaries when enabling/disabling remapping logic to handle in-flight transactions appropriately. Update root table and interrupt remap table pointers only when necessary and ensure consistency in remapping results.
Ensure deterministic transaction boundaries when enabling/disabling remapping logic to handle in-flight transactions appropriately. Update root table and interrupt remap table pointers only when necessary and ensure consistency in remapping results.
Key Data from Tables
Indicates whether translation hardware is enabled. Indicates the status of the root-table pointer operation. Indicates completion of the queued invalidation enable operation. Indicates completion of the interrupt-remap enable operation.
Indicates whether translation hardware is enabled. Indicates the status of the root-table pointer operation. Indicates completion of the queued invalidation enable operation. Indicates completion of the interrupt-remap enable operation.
Overview
This document provides detailed technical specifications and configurations for Intel VT-d (Virtualization Technology for Directed I/O) and Integrated I/O (IIO) Configuration Registers. It includes information on fault recording, interrupt handling, memory protection, and invalidation processes.
This document provides detailed technical specifications and configurations for Intel VT-d (Virtualization Technology for Directed I/O) and Integrated I/O (IIO) Configuration Registers. It includes information on fault recording, interrupt handling, memory protection, and invalidation processes.
Fault Recording and Handling
The document describes the mechanism for detecting and recording faults in DMA-remap hardware units. It explains the use of fault recording registers and the conditions under which fault events are generated. The primary fault pending field indicates if there are pending faults, and the primary fault overflow bit signals an overflow in fault recording registers.
The document describes the mechanism for detecting and recording faults in DMA-remap hardware units. It explains the use of fault recording registers and the conditions under which fault events are generated. The primary fault pending field indicates if there are pending faults, and the primary fault overflow bit signals an overflow in fault recording registers.
Interrupt Management
The document outlines how interrupt conditions are detected and managed. It details the roles of various fields such as fault_nonisoch_msgmsk and fault_nonisoch_msi_pend in controlling interrupt message requests and handling pending interrupts.
The document outlines how interrupt conditions are detected and managed. It details the roles of various fields such as fault_nonisoch_msgmsk and fault_nonisoch_msi_pend in controlling interrupt message requests and handling pending interrupts.
Memory Protection
Intel VT-d provides mechanisms for protecting memory regions. The document specifies the configuration of protected memory regions, including low and high base and limit addresses. It restricts DMA access to these regions to ensure data integrity and security.
Intel VT-d provides mechanisms for protecting memory regions. The document specifies the configuration of protected memory regions, including low and high base and limit addresses. It restricts DMA access to these regions to ensure data integrity and security.
Invalidation Processes
The document explains the invalidation queue management, including the configuration of queue head and tail pointers. It also covers the invalidation request queue base address and size, detailing how invalidation requests are processed and completed.
The document explains the invalidation queue management, including the configuration of queue head and tail pointers. It also covers the invalidation request queue base address and size, detailing how invalidation requests are processed and completed.
Configuration Registers
Detailed descriptions of various configuration registers are provided, including their offsets, bit attributes, and default values. These registers control aspects such as interrupt remapping, fault recording, and invalidation processes.
Detailed descriptions of various configuration registers are provided, including their offsets, bit attributes, and default values. These registers control aspects such as interrupt remapping, fault recording, and invalidation processes.
Key Parameters and Limitations
The document highlights critical parameters such as interrupt address, queue size, and protected memory addresses. It also notes limitations, such as the prohibition of DMA access to protected regions and the conditions under which interrupts are masked or pending.
The document highlights critical parameters such as interrupt address, queue size, and protected memory addresses. It also notes limitations, such as the prohibition of DMA access to protected regions and the conditions under which interrupts are masked or pending.
Overview
This document provides detailed information on the Integrated I/O (IIO) Configuration Registers, focusing on the configuration and control of IOTLB invalidation requests, device identification, and memory hot-plug capabilities.
This document provides detailed information on the Integrated I/O (IIO) Configuration Registers, focusing on the configuration and control of IOTLB invalidation requests, device identification, and memory hot-plug capabilities.
IOTLB Invalidation
The IOTLB Invalidation Request Granularity (IIRG) field determines the scope of invalidation requests, with options for global, domain-selective, and page-selective invalidations. The IOTLB Actual Invalidation Granularity (IAIG) field reports the granularity at which an invalidation request was processed.
The IOTLB Invalidation Request Granularity (IIRG) field determines the scope of invalidation requests, with options for global, domain-selective, and page-selective invalidations. The IOTLB Actual Invalidation Granularity (IAIG) field reports the granularity at which an invalidation request was processed.
Device Identification
Each device has a unique vendor and device identification number, assigned by PCI-SIG to Intel. Various configuration registers such as revision ID, base class, and subclass are detailed, reflecting device capabilities and compliance with PCI Express specifications.
Each device has a unique vendor and device identification number, assigned by PCI-SIG to Intel. Various configuration registers such as revision ID, base class, and subclass are detailed, reflecting device capabilities and compliance with PCI Express specifications.
Memory Hot-Plug Capabilities
Registers control the enabling of SMI interrupts for hot-plug events and define capabilities for hot-plug operations. Slot capabilities include indicators for power, attention, and MRL sensors, which are programmed by the BIOS based on system design.
Registers control the enabling of SMI interrupts for hot-plug events and define capabilities for hot-plug operations. Slot capabilities include indicators for power, attention, and MRL sensors, which are programmed by the BIOS based on system design.
Slot Control
Slot control registers manage power and indicator states, with specific fields for electromechanical interlock and power controller control. Indicators can be set to on, off, or blink states, reflecting the latest write operations.
Slot control registers manage power and indicator states, with specific fields for electromechanical interlock and power controller control. Indicators can be set to on, off, or blink states, reflecting the latest write operations.
Overview
This document provides detailed technical specifications and configuration registers for Integrated I/O (IIO) devices, focusing on hot-plug capabilities and error handling mechanisms.
This document provides detailed technical specifications and configuration registers for Integrated I/O (IIO) devices, focusing on hot-plug capabilities and error handling mechanisms.
Hot-Plug Interrupts
The document outlines various bits that enable or disable the generation of hot-plug interrupts based on different events such as presence detection, MRL sensor changes, power faults, and attention button presses. Each bit can be set to enable (1) or disable (0) the corresponding interrupt.
The document outlines various bits that enable or disable the generation of hot-plug interrupts based on different events such as presence detection, MRL sensor changes, power faults, and attention button presses. Each bit can be set to enable (1) or disable (0) the corresponding interrupt.
Register Descriptions
The document provides a comprehensive list of configuration registers for Device 5 Function 2, including their offsets, sizes, and default values. Key registers include:
The document provides a comprehensive list of configuration registers for Device 5 Function 2, including their offsets, sizes, and default values. Key registers include:
- vid: Vendor Identification Number, default 0x8086 for Intel.
- did: Device Identification Number, varies by function.
- pcicmd: Various control bits, mostly hardwired to 0 as they are not applicable to PCI Express.
- pcists: Status bits indicating errors and capabilities, with most bits hardwired to 0.
- ccr: Class Code Register, indicating device class and subclass.
Error Handling
The document details error severity levels for protocol errors, with levels ranging from correctable to fatal. Specific bits are designated for different error types, such as protocol parity errors and overflow/underflow conditions.
The document details error severity levels for protocol errors, with levels ranging from correctable to fatal. Specific bits are designated for different error types, such as protocol parity errors and overflow/underflow conditions.
Device Capabilities
The document specifies the capabilities of the device, including PCI Express capability ID and version, as well as the presence of a capabilities list structure.
The document specifies the capabilities of the device, including PCI Express capability ID and version, as well as the presence of a capabilities list structure.
Configuration and Control
Various control registers are described, including those for alarm settings, program sequences, and power state delays. These registers allow for detailed configuration of device behavior.
Various control registers are described, including those for alarm settings, program sequences, and power state delays. These registers allow for detailed configuration of device behavior.
Overview
This document provides detailed information on the Integrated I/O (IIO) Configuration Registers, focusing on error severity levels, error mapping, and control registers. It outlines how errors are categorized, reported, and managed within the system.
This document provides detailed information on the Integrated I/O (IIO) Configuration Registers, focusing on error severity levels, error mapping, and control registers. It outlines how errors are categorized, reported, and managed within the system.
Error Severity Levels
Errors are classified into three severity levels: Correctable (Level 0), Recoverable (Level 1), and Fatal (Level 2). A reserved state is also noted. Registers such as iioerrsv and mierrsv are used to associate detected errors with these severity levels.
Errors are classified into three severity levels: Correctable (Level 0), Recoverable (Level 1), and Fatal (Level 2). A reserved state is also noted. Registers such as iioerrsv and mierrsv are used to associate detected errors with these severity levels.
Error Mapping and System Events
The pcierrsv register allows remapping of PCI-E errors to IIO error severity levels. The sysmap register maps error severity to system events, determining the type of system response generated (e.g., NMI, SMIPMI).
The pcierrsv register allows remapping of PCI-E errors to IIO error severity levels. The sysmap register maps error severity to system events, determining the type of system response generated (e.g., NMI, SMIPMI).
Viral State and Error Pin Control
The viral register provides options to generate alerts upon detecting fatal errors. The errpinctl register configures error pins based on detected error severity, allowing for assertion or de-assertion of error pins.
The viral register provides options to generate alerts upon detecting fatal errors. The errpinctl register configures error pins based on detected error severity, allowing for assertion or de-assertion of error pins.
Error Status and Control
Registers like errpinsts and errpindat reflect the state of error pin assertions and provide data values for general-purpose outputs. The gcerrst and gcnerrst registers indicate corrected and non-fatal errors reported to the IIO global error logic.
Registers like errpinsts and errpindat reflect the state of error pin assertions and provide data values for general-purpose outputs. The gcerrst and gcnerrst registers indicate corrected and non-fatal errors reported to the IIO global error logic.
VPP Control and Status
The vppctl register defines control commands for PCA9555, including enabling VPP functions for root ports. The vppfreq register specifies timing parameters for VPP operations, such as pulse filter and hold time settings.
The vppctl register defines control commands for PCA9555, including enabling VPP functions for root ports. The vppfreq register specifies timing parameters for VPP operations, such as pulse filter and hold time settings.
Miscellaneous Controls
Registers like vppmem and vpp_inverts manage memory channel configurations and signal inversions. The miscprivc and gcerrst registers handle miscellaneous error reporting and global corrected error status.
Registers like vppmem and vpp_inverts manage memory channel configurations and signal inversions. The miscprivc and gcerrst registers handle miscellaneous error reporting and global corrected error status.
Conclusion
The document provides a comprehensive guide to configuring and managing error detection and reporting within the IIO framework, emphasizing the importance of proper error severity mapping and system response configuration.
The document provides a comprehensive guide to configuring and managing error detection and reporting within the IIO framework, emphasizing the importance of proper error severity mapping and system response configuration.
I/O Interrupt Source Register 1 (iointsrc1)
This section describes the I/O Interrupt Source Register 1, which is responsible for managing interrupt sources. The register is located at offset 0x2a4 and includes 21 bits (20:0) that are read-write volatile (RW-V) with a default value of 0x0. Each bit corresponds to a specific interrupt source, such as INTA Root Port Core, INTB ME KT, and others, up to INTA Port 3c.
This section describes the I/O Interrupt Source Register 1, which is responsible for managing interrupt sources. The register is located at offset 0x2a4 and includes 21 bits (20:0) that are read-write volatile (RW-V) with a default value of 0x0. Each bit corresponds to a specific interrupt source, such as INTA Root Port Core, INTB ME KT, and others, up to INTA Port 3c.
Remote I/O Interrupt Count (ioremintcnt)
This register, located at offset 0x2a8, counts the number of remote interrupts received. It is a 32-bit read-write volatile (RW-V) register with a default value of 0x0.
This register, located at offset 0x2a8, counts the number of remote interrupts received. It is a 32-bit read-write volatile (RW-V) register with a default value of 0x0.
Remote I/O GPE Count (ioremgpecnt)
Located at offset 0x2ac, this register tracks the number of remote General Purpose Events (GPEs) received. It includes fields for remote HPGPEs, PMGPEs, and GPEs, each 8 bits wide and RW-V with a default of 0x0.
Located at offset 0x2ac, this register tracks the number of remote General Purpose Events (GPEs) received. It includes fields for remote HPGPEs, PMGPEs, and GPEs, each 8 bits wide and RW-V with a default of 0x0.
FauxGV
This register, at offset 0x2c4, enables Fault GV. It is a single-bit read-write sticky low (RWS_L) register with a default of 0x0.
This register, at offset 0x2c4, enables Fault GV. It is a single-bit read-write sticky low (RWS_L) register with a default of 0x0.
I/OxAPIC Configuration
The I/OxAPIC has a direct memory-mapped space used to access redirection table entries. Access is limited to aligned Dword reads and writes, with offsets up to 0xFFF accessible via MBAR. The Index Register (offset 0x0) selects the indirect register for manipulation, while the Window Register (offset 0x10) holds data for indirect register access. The EOI Register (offset 0x40) converts level interrupts to edge-triggered MSI interrupts.
The I/OxAPIC has a direct memory-mapped space used to access redirection table entries. Access is limited to aligned Dword reads and writes, with offsets up to 0xFFF accessible via MBAR. The Index Register (offset 0x0) selects the indirect register for manipulation, while the Window Register (offset 0x10) holds data for indirect register access. The EOI Register (offset 0x40) converts level interrupts to edge-triggered MSI interrupts.
Window 0 Register Address Map
This section provides a detailed map of the Window 0 Register, including APIC ID, version, arbitration ID, and boot configuration. The APIC ID allows for up to 16 unique IDs, while the version and arbitration ID are legacy fields. The boot configuration indicates FSB delivery mode.
This section provides a detailed map of the Window 0 Register, including APIC ID, version, arbitration ID, and boot configuration. The APIC ID allows for up to 16 unique IDs, while the version and arbitration ID are legacy fields. The boot configuration indicates FSB delivery mode.
Redirection Table Low/High (rtl/rth) Registers
These registers, located at various offsets, are used to construct MSI interrupts. They include fields for disabling flushing, masking interrupts, trigger mode, and delivery status. The mask bit controls whether interrupts are delivered, and the trigger mode can be edge or level sensitive.
These registers, located at various offsets, are used to construct MSI interrupts. They include fields for disabling flushing, masking interrupts, trigger mode, and delivery status. The mask bit controls whether interrupts are delivered, and the trigger mode can be edge or level sensitive.
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Catalog excerpts
Intel® Core™ i7 Processor Family for LGA2011 Socket Datasheet – Volume 2 of 2 Supporting Desktop Intel® Core™ i7-4960X Extreme Edition Processor Series for the LGA2011 Socket Supporting Desktop Intel® Core™ i7-49xx and i7-48xx Processor Series for the LGA2011 Socket
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INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Legal Lines...
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Revision History Revision Number 001 Initial release
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Introduction This document is Volume 2 of 2 of the datasheet for the Intel® Core™ i7 processor family for LGA2011 Socket. Volume 2 provides register information for these processors. Volume 2 of 2 describes the Configuration Status Registers (CSRs) of each individual functional block in Uncore logic. The processor contains one or more PCI devices within each individual functional block. CSRs are the basic hardware elements that configure the Uncore logic to support various system topologies, memory configuration, and densities. The processor family contains one or more PCI devices within a single...
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Document Terminology Processor Terminology (Sheet 1 of 2) Terminology Third generation Double Data Rate SDRAM memory technology that is the successor to DDR2 SDRAM Direct Memory Access Direct Media Interface 2 Digital Thermal Sensor Enhanced Intel® SpeedStep® Technology Intel technology that allows the operating system to reduce power consumption when performance is not needed. The Execute Disable bit allows memory to be marked as executable or nonexecutable–when combined with a supporting operating system. If code attempts to run in non-executable memory the processor raises an error to the...
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Processor Terminology (Sheet 2 of 2) Terminology Power Control Unit Platform Environment Control Interface 64-bit, single-core or multi-core component (package) Processor Core The term “processor core” refers to silicon die itself which can contain multiple execution cores. Each execution core has an instruction cache, data cache, and 256KB L2 cache. All execution cores share the L3 cache. A unit of DRAM connecting four to eight devices in parallel. These devices are usually, but not always, mounted on a single side of a DDR3 DIMM. Processor interconnect between the different Uncore modules Indicate...
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Related Documents Refer to the following documents for additional information. Processor Documents Document Document Number/ Location Intel® Core™ i7 Processor Family for the LGA2011 Socket Datasheet, Volume 1 Desktop Intel Core™ i7 Processor Family for the LGA2011 Thermal Mechanical Specification and Design Guide Intel® Core™ i7 Processor Family for the LGA2011 Socket Specification Update Intel® X79 Express Chipset Datasheet Intel® X79 Express Chipset Thermal Mechanical Specifications and Design Guide Advanced Configuration and Power Interface Specification 3.0 http://www.pcisig.com/ specifications...
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Registers Overview and Configuration Process Registers Overview and Configuration Process This chapter covers • • • • Platform Configuration Structure Configuration Register Rules Register Terminology Notational Conventions Platform Configuration Structure The DMI2 physically connects the processor and the PCH. From a configuration standpoint the DMI2 is a logical extension of PCI Bus 0. DMI2 and the internal devices in the processor IIO and PCH logically constitute PCI Bus 0 to configuration software. As a result, all devices internal to the processor and the PCH appear to be on PCI Bus 0. Processor...
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Registers Overview and Configuration Process • Device 0: DMI2 Root Port. Logically this appears as a PCI device residing on PCI Bus 0. Device 0 contains the standard PCI header registers, extended PCI configuration registers and DMI2 device specific configuration registers. • Device 1: PCI Express* Root Port 1a, 1b. Logically this appears as a “virtual” PCI-to-PCI bridge residing on PCI Bus 0 and is compliant with PCI Express* Local Bus Specification Revision 2.0. Device 1 contains the standard PCI Express*/PCI configuration registers including PCI Express* Memory Address Mapping registers. It...
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Registers Overview and Configuration Process Processor Uncore Devices Map Bus = CPUBUSNO (1)* Power Control Unit (PCU) (Device 10, Function 0‐ 4) Integrated Memory Controller (Device 15 General Registers, TAD Rank and Timings, Device 16 Thermal Control and Test Registers) Performance Monitoring (Device 14,16,19) • Device 10: Processor Power Control Unit. Device 10, Function 0-4 contains the configurable PCU registers. • Device 11: Processor Interrupt Event Handling (UBox). Device 11, Function 0 contains the processor Interrupt Control Registers. Device 11, Function 3 contains the Semaphore...
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Registers Overview and Configuration Process • Device 19: Processor Performance Monitoring and Ring. Device 19 Function 0 contains the processor ring to PCI Express agent. Device 19, Function 1 contains the processor Ring to PCI Express performance monitoring registers. Device 19, Function 4 -6 contains the processor performance monitoring registers. • Device 22: Processor Core Broadcast. Device 22 Function 1-2 contains the Caching agent broadcast configuration registers for the Memory Controller. Device 22 Function 0 contains the System Address Decode Registers. Configuration Register Rules...
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Registers Overview and Configuration Process Device Mapping Each component in the processor is uniquely identified by a PCI bus address consisting of Bus Number, Device Number, and Function Number. Device configuration is based on the PCI Type 0 configuration conventions. All processor registers appear on the PCI bus assigned for the processor socket. Bus number is derived by the maximum bus range setting and processor socket number. Functions Specifically Handled by the Processor (Sheet 1 of 2) Register Group x4 Link from Processor to PCH Device 0 will work as a x4 PCI Express Port PCI Express...
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