Desktop 3rd Gen Intel® Core? Processor Family: Datasheet, Vol. 1
Desktop 3rd Gen Intel® Core? Processor Family: Datasheet, Vol. 1
This document is a datasheet for the 3rd Generation Intel® Core™, Pentium®, and Celeron® Processor Families, providing detailed specifications and features. It includes information on supported technologies, interfaces, power management, and processor compatibility.
The processors support various technologies such as Intel® Virtualization Technology, Intel® Trusted Execution Technology, Hyper-Threading Technology, and Turbo Boost Technology. These technologies enhance performance, security, and power efficiency.
The datasheet details several interfaces including System Memory Support, PCI Express, Direct Media Interface (DMI), and Platform Environment Control Interface (PECI). Each interface section provides information on architecture, configuration, and compatibility.
Power management features include support for Advanced Configuration and Power Interface (ACPI) states, processor core and package idle states, and thermal management. These features aim to optimize power consumption and thermal performance.
The document outlines various Intel technologies such as Intel® Virtualization Technology for IA-32 and Intel® 64 architectures, Intel® Trusted Execution Technology, and Intel® Advanced Vector Extensions. These technologies provide enhanced virtualization, security, and computational capabilities.
Security features include Intel® Advanced Encryption Standard New Instructions (AES-NI) and other cryptographic instructions like PCLMULQDQ and RDRAND, which enhance data encryption and security.
This datasheet provides comprehensive technical details necessary for understanding the capabilities and requirements of the 3rd Generation Intel® processors. It is essential for designers and engineers to ensure compatibility and optimal performance in their systems.
The document provides detailed specifications for various processors in the Desktop 3rd Generation Intel® Core™, Intel® Pentium®, and Intel® Celeron® families. It includes information on TDP, frequency ranges, and thermal specifications for each processor model.
The document outlines the platform requirements for compatibility between 2nd and 3rd Generation Intel® Core™ processors. It includes a compatibility diagram detailing voltage and signal requirements for different processor generations.
A comprehensive glossary of terms related to processor technology is provided, including definitions for ACPI, DDR3, Intel® Virtualization Technology, and more.
The document references additional resources and specifications, such as datasheets and architecture manuals, for further information on Intel processors.
The document outlines memory specifications for desktop and AIO systems, detailing timings for different frequencies (1333 and 1600 MHz) and modes (1N/2N). It describes Dual-Channel Symmetric Mode, which maximizes performance by interleaving addresses between channels, allowing simultaneous data retrieval.
Memory frequency and latency are determined by the slowest DIMM module. In a Two DIMM Per Channel configuration, the furthest DIMM from the processor must be populated first.
Includes Just-in-Time Command Scheduling, Command Overlap, and Out-of-Order Scheduling to optimize bandwidth and reduce latency. Data Scrambling is used to minimize di/dt impact on DDR3 VRs.
The processor can internally generate DDR3 Reference Voltage for read and write operations, optimizing voltage and signal margins through advanced training procedures.
The PCI Express interface supports Gen 3 speed, offering twice the bandwidth per lane compared to Gen 2. It maintains compatibility with existing applications and drivers, using a 128/130b encoding scheme to reduce overhead.
Divided into Transaction, Data Link, and Physical Layers, it uses packets to communicate information. The Transaction Layer manages TLPs, the Data Link Layer handles link management and error correction, and the Physical Layer manages interface operation.
DMI connects the processor and PCH, supporting only DMI x4 configuration. A DMI link down is a fatal error, preventing data corruption by not allowing link retraining.
Features a new architecture with 3D compute elements and a multi-format decode/encode pipeline. The 3D engine supports up to 16 Execution Units and includes enhancements for video quality and power management.
Includes Vertex Fetch, Vertex Shader, Geometry Shader, Clip, Strips and Fans, and Windower/IZ stages, each performing specific functions to optimize 3D rendering and processing.
The Windower removes failing pixels and reduces processing overhead, using parameters from the SF unit for rasterization. It can perform dithering to enhance resolution in low-bpp channels. The Video Engine in Intel Processor Graphics supports high-quality decode and encode of media content, including AVC/H.264, VC-1, and MPEG-2, with features like frame rate conversion and image stabilization.
The 2D Engine fetches and processes raw data into images for display, using Planes, Pipes, and Ports. It supports three simultaneous display configurations. The BLT engine accelerates GUI operations, supporting data transfers and logical operations. Display components include Display Planes, Pipes, and Ports, with support for multiple display configurations and interfaces like HDMI and DVI.
Intel FDI is a proprietary link for display traffic, supporting multiple independent channels for display configurations. It features dynamic scaling and a common reference clock, transporting data at 2.7 Gbps.
The processor supports simultaneous use of the Processor Graphics Controller and a PCI Express Graphics device, with limitations on "drag and drop" between monitors. The PECI interface allows communication of thermal data for fan speed control.
Intel VT allows multiple operating systems to run on a single system, enhancing virtualization performance and security. Features include Extended Page Tables, Virtual Processor IDs, and Descriptor-Table Exiting. Intel VT-d supports domain-based isolation and hardware-based virtualization, with features like DMA remap engines and interrupt remapping.
Intel TXT provides platform-level enhancements for creating trusted platforms, ensuring the authenticity and resistance to changes in the controlling environment.
This technology allows a single execution core to function as two logical processors, sharing some resources but maintaining separate architectural states. It requires BIOS and operating system support and is recommended for use with certain Windows operating systems.
This feature allows processor cores to run faster than their rated frequency if operating below power, temperature, and current limits, enhancing performance for both multi-threaded and single-threaded workloads. It dynamically adjusts frequency based on workload and thermal conditions.
Intel AVX extends the Intel SSE from 128-bit to 256-bit vectors, improving performance for applications requiring vector floating-point operations. It includes new instructions for better data management and processing efficiency.
- Intel AES-NI: A set of instructions for fast and secure AES encryption and decryption, supporting various cryptographic applications.
- PCLMULQDQ Instruction: Supports carry-less multiplication, essential for cryptographic systems, enhancing secure computing performance.
- RDRAND Instruction: Provides a high-quality random number generation mechanism for cryptographic key generation.
The x2APIC architecture extends xAPIC, enhancing interrupt delivery and processor addressability. It supports backward compatibility and forward extendibility, requiring new operating system and BIOS support.
This mechanism blocks malicious software attacks from user mode code, enhancing system protection against viruses and unwanted code.
Enhances power-performance by routing interrupts based on core sleep states, optimizing energy savings and performance in high interrupt scenarios.
The document outlines various power management states, including ACPI states, processor core/package idle states, and interface state combinations. These states manage power consumption and performance across different system components.
The document outlines various power states and management techniques for processors, focusing on optimizing performance and power efficiency. It details the different power states (G0, G1, G2, G3) and their corresponding actions, such as auto-halt, deep sleep, and power-off modes.
Enhanced Intel SpeedStep Technology dynamically adjusts processor frequency and voltage based on workload, defined by ACPI as P-states. The technology allows for multiple frequency and voltage points, controlled via software, to optimize performance and power efficiency. Transitions between P-states are managed to ensure smooth operation.
When idle, processors enter low-power states (C-states) to conserve energy. Higher C-states offer more power savings but have longer entry and exit latencies. The document emphasizes the importance of enabling all low-power states for long-term reliability.
Software can request low-power states using MWAIT and HLT instructions, with legacy support through ACPI-defined I/O reads. The BIOS can configure these requests to emulate MWAIT functionality.
Core C-states are determined by the lowest numerical thread state. The document describes the conditions for entering and exiting various core C-states, such as C0, C1/C1E, C3, and C6, and the implications for power management.
Package C-states are determined by the lowest core C-state among all cores. The document outlines the rules for entering and exiting package C-states, including C0, C1/C1E, C3, and C6, and the conditions under which these states are achieved.
The IMC manages power during normal operation and low-power states. Unused memory outputs are disabled to reduce power consumption and improve signal quality. The document also covers DRAM power management, detailing different power-down modes and their impact on power savings and wakeup times.
The document outlines various power down configurations for CKE (Clock Enable) in DDR memory systems. The options include no power down, Active Power Down (APD), Precharge Power Down (PPD), and DLL-off modes. Each rank has an idle counter that triggers power down when no transactions occur. The choice of power mode depends on system requirements for performance, power consumption, and thermal management. BIOS settings and idle timer configurations influence power management.
During power-up, CKE is crucial for SDRAM initialization. Intel Rapid Memory Power Management (RMPM) uses self-refresh in low-power states to save energy, influenced by graphics and I/O device activity.
Dynamic power down is employed during normal operations, with options for active or precharge power down. Precharge power down offers more savings but impacts performance.
Unused signals should be disabled to save power and reduce interference. Electrical Power Gating (EPG) is supported for DDR I/O during certain power states, maintaining essential control registers active.
Active power management is supported using L0s and L1 states, with inputs and outputs disabled in L2/L3 Ready state. Disabling ASPM may increase power consumption.
Intel RMPM and Graphics Performance Modulation Technology (GPMT) manage power in graphics adapters by adjusting render frequency and voltage. Render C-State optimizes power during idle times, and Intel Smart 2D Display Technology (S2DDT) reduces memory traffic for display refresh.
The document describes processor signals, categorized by interface or function, including PCI Express, DMI, CMOS, and DDR3 signals. Each signal type is detailed with its function and buffer type.
DDR3 reference voltage signals are used for the DDR3 controller and DIMM DQ voltage reference. These signals ensure optimized voltage margins with a nominal source impedance of 150Ω and a step size of 7.7 mV for DDR3.
Configuration signals (CFG) have default values and are used for PCI Express lane numbering and bifurcation. Other signals include power management sync, platform reset, and reserved signals that should remain unconnected.
PCI Express signals include current and resistance compensation, as well as transmit and receive differential pairs. The Intel Flexible Display Interface (FDI) includes frame and line sync signals for display pipes and hot-plug interrupts.
DMI signals facilitate processor to PCH communication, while PLL signals provide clock inputs for processor operations.
TAP signals support debugging and performance monitoring. Error signals like CATERR# and thermal protection signals like PROCHOT# and THERMTRIP# manage system errors and overheating.
Power sequencing signals ensure stable power supply conditions. Processor power signals include core power rail and I/O supply voltages.
Power and ground lands must be connected to respective power planes. Decoupling guidelines emphasize the need for adequate bulk decoupling to manage current swings. Voltage rail decoupling requires low ESR and interconnect resistance.
The processor uses a differential clock for frequency generation, with an internal PLL for clock multiplication. Voltage identification is managed through a serial interface for automatic voltage selection.
The document outlines the VID specifications for voltage regulation in processors. A '1' indicates a high voltage level, while a '0' indicates a low voltage level. If the voltage regulation circuit cannot supply the requested voltage, the voltage regulator must disable itself. VID signals are CMOS push/pull drivers, and their DC specifications are detailed in Table 7-8. VID codes may change due to temperature or current load changes to minimize power consumption. A voltage range is provided in Table 7-4, allowing one voltage regulator to operate with all supported frequencies. Individual processor VID values may vary, even at the same core frequency, as shown in Table 7-4. The processor can operate while transitioning to an adjacent VID and its associated voltage, representing a DC shift in the loadline.
The VCCSA is configured by the processor output land VCCSA_VID, with a default logic state of low for 2nd and 3rd generation Desktop Core processors, configuring VCCSA to 0.925 V.
Reserved signals should not be connected, while RSVD_TP signals must be routed to a test point. Arbitrary connections may result in component malfunction. Unused inputs or bi-directional signals should be connected to an appropriate signal level for reliable operation.
Signals are grouped by buffer type and characteristics, with differential signals and selected DDR3 and Control Sideband signals having On-Die Termination (ODT) resistors. Some signals without ODT need termination on the board.
Intel recommends the processor be first in the TAP chain, followed by other components. A translation buffer should be used unless other components can accept the appropriate voltage input. The processor supports Boundary Scan (JTAG) IEEE 1149.1-2001 and IEEE 1149.6-2003 standards.
Environmental storage conditions define temperature and relative humidity limits for devices stored in moisture barrier bags. Table 7-3 specifies absolute maximum and minimum storage temperature limits. Adhering to these specifications is crucial for long-term reliability.
This section provides a detailed list of processor lands categorized by their names, land numbers, buffer types, and directions. The document includes tables that specify the power (PWR), ground (GND), and analog signals for various processor lands. Key categories include VCCAXG, VCCIO, VCCPLL, VCCSA, VDDQ, and VSS, each associated with specific land numbers and buffer types.
The document explains the concept of DDR Data Swizzling, which is a technique used to enhance memory performance and timing by rearranging data pins. This process is transparent to the operating system and software but is crucial for debugging purposes. The document provides swizzling tables for Channel A and Channel B, detailing the mapping between land names and memory controller (MC) land names. This information is essential for design engineers when placing DIMM logic analyzers to ensure efficient memory debugging.
Catalog excerpts
Desktop 3rd Generation Intel® Core™ Processor Family, Desktop Intel® Pentium® Processor Family, and Desktop Intel® Celeron® Processor Family Datasheet – Volume 1 of 2
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INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. A "Mission...
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Revision History Revision Number Revision Date • Initial release • Updated Section 1.2.2, PCI Express* 003 • Updated Section 2.1.1, System Memory Technology Supported • Updated Table 7-4, “Processor Core Active and Idle Mode DC Voltage and Current Specifications”. Added 65 W to 2011C. • Minor edits throughout for clarity 004 • Added Desktop 3rd Generation Intel® Core™ i3-3210 processor 005 • Added Desktop Intel® Pentium® G2130, G2020, G2020T, G2010 processor • Added Desktop Intel® Celeron® G1620, G1610, G1610T processor 006 • Added Desktop 3rd Generation Intel® Core™ i3-3250, i3-3250T, i3-3245...
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Introduction The Desktop 3rd Generation Intel® Core™ processor family, Desktop Intel® Pentium® processor family, and Desktop Intel® Celeron® processor family are the next generation of 64-bit, multi-core processors built on 22-nanometer process technology. The processors are designed for a two-chip platform. The two-chip platform consists of a processor and a Platform Controller Hub (PCH) and enables higher performance, lower cost, easier validation, and improved x-y footprint. The processor includes an Integrated Display Engine, Processor Graphics, PCI Express ports, and an Integrated Memory...
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Desktop Processor Platform Intel® Processor PECI Intel® Flexible Display Interface Intel® Management Engine Intel® 6/7 Series Chipset Families WiFi / WiMax Gigabit Network Connection Note: 1. USB 3.0 is supported on the Intel® 7 Series Chipset family only.
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Processor Feature Details • • • • Four or two execution cores A 32-KB instruction and 32-KB data first-level cache (L1) for each core A 256-KB shared instruction / data second-level cache (L2) for each core Up to 8-MB shared instruction / data third-level cache (L3), shared among all cores Supported Technologies • Intel® Virtualization Technology (Intel® VT) for Directed I/O (Intel® VT-d) • Intel® Virtualization Technology (Intel® VT) for IA-32, Intel® 64 and Intel® Architecture (Intel® VT-x) Intel® Active Management Technology (Intel® AMT) 8.0 • Intel® Trusted Execution Technology (Intel® TXT)...
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• Support memory configurations that mix DDR3 DIMMs/DRAMs with DDR3L DIMMs/DRAMs running at 1.5 V • The type of the DIMM modules supported by the processor is dependent on the PCH SKU in the target platform: — Desktop PCH platforms support non-ECC UDIMMs only — All In One platforms (AIO) support SO-DIMMs • Theoretical Maximum Memory Bandwidth: — 10.6 GB/s in single-channel mode or 21.3 GB/s in dual-channel mode assuming DDR3 1333 MT/s — 12.8 GB/s in single-channel mode or 25.6 GB/s in dual-channel mode assuming DDR3 1600 MT/s • Processor on-die Reference Voltage (VREF) generation for both DDR3...
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to transmit data across this interface. This also does not account for packet overhead and link maintenance. • Maximum theoretical bandwidth on the interface of 8 GB/s in each direction simultaneously, for an aggregate of 16 GB/s when x16 Gen 2 • Gen 3 raw bit-rate on the data pins of 8.0 GT/s, resulting in a real bandwidth per pair of 984 MB/s using 128b/130b encoding to transmit data across this interface. This also does not account for packet overhead and link maintenance. • Maximum theoretical bandwidth on the interface of 16 GB/s in each direction simultaneously, for an aggregate of 32 GB/s...
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Direct Media Interface (DMI) • DMI 2.0 support • Four lanes in each direction • 5 GT/s point-to-point DMI interface to PCH is supported • Raw bit-rate on the data pins of 5.0 Gb/s, resulting in a real bandwidth per pair of 500 MB/s given the 8b/10b encoding used to transmit data across this interface. Does not account for packet overhead and link maintenance. • Maximum theoretical bandwidth on interface of 2 GB/s in each direction simultaneously, for an aggregate of 4 GB/s when DMI x4 • Shares 100-MHz PCI Express* reference clock • 64-bit downstream address format; however, the processor never...
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• DirectX* Video Acceleration (DXVA) support for accelerating video processing — Full AVC/VC1/MPEG2 HW Decode • Advanced Scheduler 2.0, 1.0, XPDM support • Windows* 7, Windows* XP, OSX, Linux OS Support • DirectX* 11, DirectX* 10.1, DirectX* 10, DirectX* 9 support • OpenGL* 3.0 support • Switchable Graphics support on Desktop AIO platforms with MxM solutions only Intel® Flexible Display Interface (Intel® FDI) • For SKUs with graphics, carries display traffic from the Processor Graphics in the processor to the legacy display connectors in the PCH • Based on DisplayPort standard • The two Intel...
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Direct Media Interface (DMI) • L0s and L1 ASPM power management capability Processor Graphics Controller (GT) • • • • Intel® Rapid Memory Power Management (Intel® RMPM) – CxSR Intel® Graphics Performance Modulation Technology (Intel® GPMT) Intel® Smart 2D Display Technology (Intel® S2DDT) Graphics Render C-State (RC6) Thermal Management Support • Digital Thermal Sensor • Intel Adaptive Thermal Monitor • THERMTRIP# and PROCHOT# support • On-Demand Mode • Memory Thermal Throttling • External Thermal Sensor (TS-on-DIMM and TS-on-Board) • Render Thermal Throttling • Fan speed control with DTS Desktop...
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