c600-series
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Intel® C600 Series Chipset Data Sheet March 2012 Document Number: 326514-001

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INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. UNLESS...

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Revision History Description 001 Note: • Initial Release Not all features are available on all PCH SKUs. See Section 1.3 for more details. § 36 Date March 2012

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Intel® C600 Series Chipset Features • Direct Media Interface • USB — NEW: Up to 20 Gb/s each direction, full duplex — Lane reversal supported — Transparent to software • PCI Express* Root Ports — 8 PCI Express* root ports — NEW: Supports PCI Express* 2.0 running at up to 5.0 GT/s — Ports 1-4 and ports 5-8 can independently be configured to support eight x1s, two x4s, two x2s, and four x1s, or one x4 and four x1 port widths. — Module based hot-plug supported (i.e. ExpressCard*) — Lane reversal supported on x4 configuration • NEW: PCI Express* Uplink Port — SKU specific x4 PCI Express*...

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• Intel® High Definition Audio Interface — PCI Express* endpoint — Independent Bus Master logic for eight general purpose streams: four input and four output — Support four external Codecs — Supports variable length stream slots — Supports multichannel, 32-bit sample depth, 192 kHz sample rate output — Provides mic array support — Allows for non-48 kHz sampling output • Support for ACPI Device States — Four PWM signals and Eight TACH signals • Simple Serial Transport (SST) 1.0 Bus and Platform Environmental Control Interface (PECI) • PCI Bus Interface • • • • • — Supports PCI Rev 2.3...

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1 Introduction 1.1 About This Manual This manual is intended for Original Equipment Manufacturers and BIOS vendors creating Intel® C600 Series Chipset based products (See Section 1.3 for currently defined SKUs). Note: Throughout this manual, Platform Controller Hub(PCH) is used as a general term and refers to all Intel® C600 Series Chipset SKUs, unless specifically noted otherwise. This manual assumes a working knowledge of the vocabulary and principles of PCI Express*, USB, AHCI, SATA, Intel® High Definition Audio (Intel® HD Audio), SMBus, PCI, ACPI and LPC. Although some details of these...

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Table 1-1. Industry Specifications (Sheet 2 of 2) Specification Location SFF-8485 Specification for Serial GPIO (SGPIO) Bus, Revision 0.7 ftp://ftp.seagate.com/sff/SFF-8485.PDF Advanced Host Controller Interface specification for Serial ATA, Revision 1.3 http://www.intel.com/technology/serialata/ ahci.htm Intel® High Definition Audio Specification, Revision 1.0a http://www.intel.com/standards/hdaudio/ MultiProcessor Specification http://www.intel.com/design/pentium/datashts/ 242016.HTM Chapter 1. Introduction Chapter 1 introduces the PCH and provides information on manual organization and...

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Chapter 12. Integrated LAN Controller Registers Chapter 12 provides a detailed description of all registers that reside in the PCH’s integrated LAN controller. The integrated LAN Controller resides at Device 25, Function 0 (D25:F0). Chapter 13. LPC Bridge Registers Chapter 13 provides a detailed description of all registers that reside in the LPC bridge. This bridge resides at Device 31, Function 0 (D31:F0). This function contains registers for many different units within the PCH including DMA, Timers, Interrupts, Processor Interface, GPIO, Power Management, System Management and RTC....

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Chapter 24. Intel® Management Engine (Intel® ME) Chapter 24 provides a detailed description of all registers that reside in the thermal sensors PCI configuration space. The registers reside at Device 31, Function 6 (D31:F6). Chapter 25. Upstream PCIe* Interface Registers (PCH -D/T SKUs only) Chapter 25 provides a detailed description of all registers that reside in the upstream PCI Express* controller. This controller resides at Bus N, Device 0, Function 0 (BN:D0:F0). Chapter 26. PCIe Virtual Root/Switch Port Interface Registers Chapter 26 provides a detailed description of all registers...

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• JTAG Boundary Scan support The PCH incorporates a variety of PCI devices and functions. Refer to Table 9-1 for details. 1.2.1 Capability Overview The following sub-sections provide an overview of the PCH capabilities. Digital Media Interface (DMI) Digital Media Interface (DMI) is the chip-to-chip connection between the processor and PCH. This high-speed interface integrates advanced priority-based servicing allowing for concurrent traffic and true isochronous transfer capabilities. Base functionality is completely software-transparent, permitting current and legacy software to operate...

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AHCI The PCH provides hardware support for Advanced Host Controller Interface (AHCI), a standardized programming interface for SATA host controllers. Platforms supporting AHCI may take advantage of performance features such as no master/slave designation for SATA devices—each device is treated as a master—and hardwareassisted native command queuing. AHCI also provides usability enhancements such as Hot-Plug. AHCI requires appropriate software support (for example, an AHCI driver) and for some features, hardware support in the SATA device or additional platform hardware. Please see Section...

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The timer/counter block contains three counters that are equivalent in function to those found in one 8254 programmable interval timer. These three counters are combined to provide the system timer function, and speaker tone. The 14.31818 MHz oscillator input provides the clock source for these three counters. The PCHPCH provides an ISA-Compatible Programmable Interrupt Controller (PIC) that incorporates the functionality of two, 8259 interrupt controllers. The two interrupt controllers are cascaded so that 14 external and two internal interrupts are possible. In addition, the PCH supports...

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