2nd Generation Intel® Core? Processor and Pentium® Processor: Specification Update
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2nd Generation Intel® Core™ Processor Family Desktop, Intel® Pentium® Processor Family Desktop, and Intel® Celeron® Processor Family Desktop Specification Update December 2013

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2nd Generation Intel® Core™ Processor Family Desktop, Intel® Pentium® Processor Family Desktop, and Intel® Celeron® Processor Family Desktop December 2013 Specification Update

2nd Generation Intel® Core™ Processor Family Desktop, Intel® Pentium® Processor Family Desktop, and Intel® Celeron® Processor Family Desktop Specification Update December 2013

Revision History Revision Initial Release Updated Processor Identification table to include the SKU information for — 2nd Generation Intel® Core™ i5-2310, i5-2405S and i3-2105 processors — Intel® Pentium® Processor G850, G840, G620 and G620T Updated Processor Identification table to include the SKU information for — 2nd Generation Intel® Core™ i5-2320, i3-2125, i3-2130 and i3-2120T processors — Intel® Pentium® Processor G860, G630 and G630T — Intel® Celeron® Processor G540, G530, G530T, G440 Added Erratum BJ96 Removed Erratum BJ73 Skipped Revision -012 Updated Erratum BJ65 Added G460...

2nd Generation Intel® Core™ Processor Family Desktop, Intel® Pentium® Processor Family Desktop, and Intel® Celeron® Processor Family Desktop Specification Update December 2013

Preface This document is an update to the specifications contained in the Affected Documents table below. This document is a compilation of device and documentation errata, specification clarifications and changes. It is intended for hardware system manufacturers and software developers of applications, operating systems or tools. Information types defined in Nomenclature are consolidated into the specification update and are no longer published in other documents. This document may also contain information that was not previously published. Affected Documents Document Number Document Title...

Nomenclature Errata are design defects or errors. These may cause the processor behavior to deviate from published specifications. Hardware and software designed to be used with any given stepping must assume that all errata documented for that stepping are present on all devices. S-Spec Number is a five-digit code used to identify products. Products are differentiated by their unique characteristics such as, core speed, L2 cache size, package type, etc. as described in the processor identification information table. Read all notes associated with each S-Spec number. Specification Changes...

Summary Tables of Changes The following tables indicate the errata, specification changes, specification clarifications, or documentation changes which apply to the processor. Intel may fix some of the errata in a future stepping of the component, and account for the other outstanding issues through documentation or specification changes as noted. These tables uses the following notations: Codes Used in Summary Tables X: Errata exists in the stepping indicated. Specification Change or Clarification that applies to this stepping. or (Blank box): This erratum is fixed in listed stepping or...

Errata (Sheet 1 of 5) Steppings Number An Enabled Debug Breakpoint or Single Step Trap May Be Taken after MOV SS/ POP SS Instruction if it is Followed by an Instruction That Signals a Floating Point Exception APIC Error “Received Illegal Vector” May be Lost An Uncorrectable Error Logged in IA32_CR_MC2_STATUS May also Result in a System Hang B0-B3 Bits in DR6 For Non-Enabled Breakpoints May be Incorrectly Set Changing the Memory Type for an In-Use Page Translation May Lead to MemoryOrdering Violations Code Segment Limit/Canonical Faults on RSM May be Serviced before Higher Priority...

Errata (Sheet 2 of 5) Steppings Number Reported Memory Type May Not Be Used to Access the VMCS and Referenced Data Structures Single Step Interrupts with Floating Point Exception Pending May Be Mishandled Storage of PEBS Record Delayed Following Execution of MOV SS or STI The Processor May Report a #TS Instead of a #GP Fault VM Exits Due to “NMI-Window Exiting” May Be Delayed by One Instruction Pending x87 FPU Exceptions (#MF) May be Signaled Earlier Than Expected Values for LBR/BTS/BTM Will be Incorrect after an Exit from SMM Unsupported PCIe* Upstream Access May Complete with an Incorrect...

Errata (Sheet 3 of 5) Steppings Number A Write to the IA32_FIXED_CTR1 MSR May Result in Incorrect Value in Certain Conditions Instruction Fetch May Cause Machine Check if Page Size and Memory Type Was Changed Without Invalidation Reception of Certain Malformed Transactions May Cause PCIe* Port to Hang Rather Than Reporting an Error PCIe* LTR Incorrectly Reported as Being Supported Performance-Counter Overflow Indication May Cause Undesired Behavior XSAVE Executed During Paging-Structure Modification May Cause Unexpected Processor Behavior C-state Exit Latencies May be Higher Than Expected...

Errata (Sheet 4 of 5) Steppings Number PCIe* Presence Detect State May Not be Accurate After a Warm Reset Display Corruption May be Seen After Graphics Voltage Rail (VCC_AXG) Power Up PCMPESTRI, PCMPESTRM, VPCMPESTRI and VPCMPESTRM Always Operate with 32-bit Length Registers VM Entries That Return From SMM Using VMLAUNCH May Not Update The Launch State of the VMCS Interrupt From Local APIC Timer May Not Be Detectable While Being Delivered An Unexpected Page Fault May Occur Following the Unmapping and Re-mapping of a Page A PCIe* Device That Initially Transmits Minimal Posted Data Credits...