2nd Generation Intel® Core™ Processor Family Mobile Datasheet, Volume 1
172Pages

Document Number: 324692-001ƒn 2nd Generation Intel® Core™ Processor Family Mobile Datasheet – Volume 1 Supporting Intel® Core™ i7 Mobile Extreme Edition Processor Series and Intel® Core™ i5 and i7 Mobile Processor Series This is Volume 1 of 2 January 2011

2 Datasheet, Volume 1 Legal Lines and Disclaimers INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT,...

10 Datasheet, Volume 1 Revision History § § Revision Number Description Date 001 • Initial Release January 2011

Datasheet, Volume 1 11 Introductionƒn 1Introduction The 2nd Generation Intel® Core™ processor family mobile is the next generation of 64- bit, multi-core mobile processor built on 32- nanometer process technology. Based on a new micro-architecture, the processor is designed for a two-chip platform. The twochip platform consists of a processor and Platform Controller Hub (PCH). The platform enables higher performance, lower cost, easier validation, and improved x-y footprint. The processor includes Integrated Display Engine, Processor Graphics and Integrated Memory Controller and is designed...

Introduction 12 Datasheet, Volume 1 Figure 1-1. 2nd Generation Intel® Core™ Extreme Edition Processor Family Mobileƒn Platform Intel® Flexible Display Int erface DMI2 x4 Discrete Graphics (PEG) Analog CRT Gigabit Network Connection USB 2.0 Intel® HD Audio FWH Super I/O Serial ATA PCI Express* 2.0 DDR3 1 x16 or 2x8 8 PCI Express* 2.0 x1 Ports (5 GT/s) SPI Digital Display x 3 PCI Express* SPI Flash x 2 LPC SMBUS 2.0 GPIO LVDS Flat Panel WiFi / WiMax Controller Link 1 Embedded Display Port Processor PECI Platform Controller Hub (PCH) Intel® Management Engine

Datasheet, Volume 1 13 Introductionƒn 1.1Processor Feature Details •Four or two execution cores •A 32-KB instruction and 32-KB data first-level cache (L1) for each core •A 256-KB shared instruction/data second-level cache (L2) for each core •Up to 8-MB shared instruction/data third-level cache (L3), shared among all cores 1.1.1Supported Technologies •Intel® Virtualization Technology for Directed I/O (Intel® VT-d) •Intel® Virtualization Technology (Intel® VT-x) •Intel® Active Management Technology 7.0 (Intel® AMT 7.0) •Intel® Trusted Execution Technology (Intel® TXT) •Intel® Streaming SIMD...

Introduction 14 Datasheet, Volume 1 •Up to 32 simultaneous open pages, 16 per channel (assuming 4 Ranks of 8 Bank Devices) •Memory organizations —Single-channel modes —Dual-channel modes - Intel® Flex Memory Technology: - Dual-channel symmetric (Interleaved) •Command launch modes of 1n/2n •On-Die Termination (ODT) •Asynchronous ODT •Intel® Fast Memory Access (Intel® FMA) —Just-in-Time Command Scheduling —Command Overlap —Out-of-Order Scheduling 1.2.2PCI Express* •The PCI Express* port(s) are fully-compliant to the PCI Express Base Specification, Revision 2.0. •Processor with mobile PCH...

Datasheet, Volume 1 15 Introductionƒn •PCI Express* extended configuration space. The first 256 bytes of configuration space aliases directly to the PCI Compatibility configuration space. The remaining portion of the fixed 4-KB block of memory-mapped space above that (starting at 100h) is known as extended configuration space. •PCI Express* Enhanced Access Mechanism; accessing the device configuration space in a flat memory mapped fashion •Automatic discovery, negotiation, and training of link out of reset •Traditional AGP style traffic (asynchronous non-snooped, PCI-X Relaxed ordering)...

Introduction 16 Datasheet, Volume 1 •64-bit downstream address format, but the processor never generates an address above 64 GB (Bits 63:36 will always be zeros) •64-bit upstream address format, but the processor responds to upstream read transactions to addresses above 64 GB (addresses where any of Bits 63:36 are nonzero) with an Unsupported Request response. Upstream write transactions to addresses above 64 GB will be dropped. •Supports the following traffic types to or from the PCH —DMI -> DRAM —DMI -> processor core (Virtual Legacy Wires (VLWs), Resetwarn, or MSIs only) —Processor core...

Datasheet, Volume 1 17 Introductionƒn 1.2.6Embedded DisplayPort* (eDP*) •Stand alone dedicated port (unlike previous generation processor that shared pins with PCIe interface) 1.2.7Intel® Flexible Display Interface (Intel® FDI) •For SKUs with graphics, carries display traffic from the Processor Graphics in the processor to the legacy display connectors in the PCH •Based on DisplayPort standard •Two independent links – one for each display pipe •Four unidirectional downstream differential transmitter pairs —Scalable down to 3X, 2X, or 1X based on actual display bandwidth requirements —Fixed...

Introduction 18 Datasheet, Volume 1 1.3.6Processor Graphics Controller •Rapid Memory Power Management RMPM – CxSR •Graphics Performance Modulation Technology (GPMT) •Intel Smart 2D Display Technology (Intel S2DDT) •Graphics Render C-State (RC6) •Intel® Seamless Display Refresh Rate Switching with eDP port 1.4Thermal Management Support •Digital Thermal Sensor •Intel® Adaptive Thermal Monitor •THERMTRIP# and PROCHOT# support •On-Demand Mode •Open and Closed Loop Throttling •Memory Thermal Throttling •External Thermal Sensor (TS-on-DIMM and TS-on-Board) •Render Thermal Throttling •Fan speed...